• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.3
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• pp.87-99
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• 2006

In this paper, we propose a method of conditional access control for encrypted SVC(scalable video coding) bitstream. The main purpose of the proposition is to provide a SVC suitable encryption algorithm and a efficient method for conditional access control using encrypted SVC bitstream. We analyzed requirements for conditional access control of a SVC bitstream. And based on the analysis, we proposed encryption algorithm suitable for SVC bitstream and a method of conditional access control of the encryped bitstream. The proposed conditional access control for encrypted SVC bitstream is performed by bitsream extraction and selective decryption. We verified the usefulness of the proposed method through experiments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.647-650
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• 2004

MAC RX FIFO은 10Gbps전용 전송속도에서 제공하는 FIFO모듈이다. 10Gbps이상의 전송속도에서는 전송부, 수신부모두 양방향 전송신가능한 Full Duplex(전이중)방식을 사용한다. 기존 FIFO의 임시 버퍼기능 뿐만 아니라 프레임 흐름 컨트롤 블록을 적용하여 전송간의 프레임 흐름제어 기능을 수행한다. 하위계층에서 MAC으로부터 전송되는 데이터는 64비트와 데이터 유효 정보를 가진 8비트 데이터 유효 정보비트를 가진다. 이렇게 전송되는 데이터는 MAC RX FIFO에 프레임단위로 저장되어 프레임간의 구분정보 Codeword프레임을 확인하여 새프레임 데이터를 확인한다. 사용자계층에는 데이터 128비트와 유효 정보비트 16비트로 사용자계층에 전송한다. 본 논문에서는 10G 전송속도을 갖는 MAC RX FIFO을 설계한다. VHDL언어를 사용하였고 ModelSim5.6a로 시뮬레이션하여 파형분석과 타이밍 분석하여 정상적인 동작을 확인한다. MAC RX FIFO는 10Gbps전송속도에서 요구되어지는 모듈에서 Flow Control, Pause프레임기능을 갖는 모듈에 적용되어 사용가능 할 것으로 사료된다.

• Information and Communications Magazine
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• v.16 no.12
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• pp.112-120
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• 1999

• Information and Communications Magazine
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• v.16 no.5
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• pp.17-27
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• 1999

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.323-329
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• 2002

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier which produces an N-bit output from a two's complement multiplication of two N bit inputs by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance(truncation error, area) was analyzed. Since the truncated Booth multiplier does not have about half the partial product generators and adders, it results an area reduction of about 35％, compared with no-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 60％, compared with conventional methods. A 16-b$\times$16-b truncated Booth multiplier core is designed on full-custom style using 0.35-${\mu}{\textrm}{m}$ CMOS technology. It has 3,000 transistors on an area of 330-${\mu}{\textrm}{m}$$\times$262-${\mu}{\textrm}{m}$ and 20-㎽ power dissipation at 3.3-V supply with 200-MHz operating frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.593-602
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• 2006

This paper propose to methodology for deciding suitable bit size that minimizes hardware complexity and performance degradation from floating-point design the fixed-point implementation of downlink traffic channel of IEEE 802.16e OFDMA TDD system. One of the major considering issues for implementing fixed-point design is to select Saturation or Quantization properly with the knowledge of signal distribution by pdf or histogram. Also, through trial and error, we should execute exhaustive computer simulation for various bit sizes, hence obtain appropriate bit size while minimizing performance degradation. We carry out computer simulation to decide the optimized bit size of downlink traffic channel under AWGN and ITU-R M.1225 Veh-A channel model.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1654-1665
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• 2008

This paper presents bit splitting methods to apply multilevel modulation to iterative codes such as turbo code, low density parity check code and turbo product code. Log-likelihood ratio method splits multilevel symbols to soft decision symbols using the received in-phase and quadrature component based on Gaussian approximation. However it is too complicate to calculate and to implement hardware due to exponential and logarithm calculation. Therefore this paper presents Euclidean, MAX, sector and center focusing method to reduce the high complexity of LLR method. Also, this paper proposes optimal soft symbol split method for three kind of iterative codes. Futhermore, 16-APSK modulator method with double ring structure for applying DVB-S2 system and 16-QAM modulator method with lattice structure for T-DMB system are also analyzed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.771-774
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• 2010

In this paper, BER performance of LDPC(Low-Density Parity-Check) decoder for WiMAX is analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by Matlab, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate(BER) performance of LDCP decoder. The parity check matrix for IEEE 802.16e standard which has block length of 2304 and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (8,6).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.607-613
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• 2008

In this paper, we investigate the performance of SMP-assisted 3GPP GERAN evolution system employing high order modulation and turbo coding. When applying the SMP which maps systematic bits into highly reliable bit positions, it is confirmed that there is the performance gain for the modulation and coding schemes of 16QAM(DAS-8) as well as 32QAM(DAS-11) by link level simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.983-987
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• 2004

Pilot symbol assisted modulation (PSAM) can be used for the channel estimation. However, imperfect channel estimates degrade the bit error rate (BER) performance. I derive the exact BER of 16-level quadrature amplitude modulated (16-QAM) orthogonal frequency division multiplexing (OFDM) systems with PSAM in time dispersive Rayleigh fading channels. In real system, there is 2.5 dB penalty in $\overline{\gamma_b}$for the same BER relative to ideal system with perfect channel estimation.