• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1185-1188
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• 2003

This paper describes a design for a 2.5Gb/s serial data link CMOS transceiver based on the InfiniBand$^{TM}$ specification. The transceiver chip integrates data serializer, line driver, Tx PLL, deserializer, clock recovery, and lock detector. The designed transceiver is fabricated in a 0.25 ${\mu}{\textrm}{m}$ CMOS mixed-signal, 1-poly, 5-metal process. The first version chip occupies a 3.0mm x 3.3mm area and consumes 450mW with 2.5V supply. In 2.5 Gbps, the output jitter of transmitter measured at the point over a 1.2m, 50Ω coaxial cable is 8.811ps(rms), 68ps(p-p). In the receiver, VCO jitter is 18.5ps(rms), 130ps(p-p), the recovered data are found equivalent to the transmitted data as expected. In the design for second version chip, the proposed clock and data recovery circuit using linear phase detector can reduce jitter in the VCO of PLL.L.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.5
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• pp.949-958
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• 2018

A voice recognition control system is a system for controlling a peripheral device by recognizing a voice. Recently, a voice recognition control system have been applied not only to smart devices but also to various environments ranging from IoT(: Internet of Things), robots, and vehicles. In such a voice recognition control system, the recognition rate is lowered due to the ambient noise in addition to the voice of the user. In this paper, we propose a dual channel acoustic beamforming hardware architecture for MEMS(: Microelectromechanical Systems) microphones to eliminate ambient noise in addition to user's voice. And the proposed hardware architecture is designed as ASIC(: Application-Specific Integrated Circuit) using TowerJazz $0.18{\mu}m$ CMOS(: Complementary Metal-Oxide Semiconductor) technology. The designed dual channel acoustic beamforming ASIC has a die size of $48mm^2$, and the directivity index of the user's voice were measured to be 4.233㏈.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.60-68
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• 2016

This paper presents a 6~18 GHz 7-bit digital-controlled attenuator. The proposed attenuator is based on switched-T architecture, but no inductor is used for minimum chip size. The designed attenuator was fabricated using $0.18{\mu}m$ CMOS process, and characterized using on-wafer testing setup. The resolution(minimum attenuation step) and the maximum attenuation range of the attenuator were measured to be 0.22 dB and 28 dB, respectively. The measured RMS attenuation error and the RMS phase error for 6~18 GHz were less than 0.26 dB and $3.2^{\circ}$, respectively. The reference state insertion loss was less than 12.4 dB at 6~18 GHz. The measured input and output return losses were better than 9.4 dB over all frequencies and attenuation states. The chip size is $0.11mm^2$ excluding pads.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.91-95
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• 2008

This paper presents a direct-conversion I/Q up-mixer block, which supports $3{\sim}5$ GHz ultra-wideband(UWB) applications. It consists of a VI converter, a double-balanced mixer, a RF amplifier, and a differential-to-single signal converter. To achieve wideband characteristics over $3{\sim}5$ GHz frequency range, the double-balanced mixer adopts a shunt-peaking load. The proposed RF amplifier can suppress unwanted common-mode input signals with high linearity. The proposed direct-conversion I/Q up-mixer block is implemented using $0.18-{\mu}m$ CMOS technology. The measured results for three channels show a power gain of $-2{\sim}-9$ dB with a gain flatness of 1dB, a maximum output power level of $-7{\sim}-14.5$ dBm, and a output return loss of more than - 8.8 dB. The current consumption of the fabricated chip is 25.2 mA from a 1.8 V power supply.

• Journal of electromagnetic engineering and science
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• v.8 no.1
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• pp.34-39
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• 2008

An RF front-end dual-conversion receiver for $3{\sim}5\;GHz$ MB-OFDM UWB systems is implemented in $0.18\;{\mu}m$ CMOS technology. The receiver includes a two-stage UWB LNA, an RF mixer, an IF I/Q mixer, and a frequency synthesizer. The proposed receiver adopts the dual-conversion architecture to mitigate the burden of design of the frequency synthesizer. Accordingly, the proposed frequency synthesizer generates four LO tones from only one VCO. The receiver front-end achieves power gain of 16.3 to 21 dB, NF of 7 to 7.6 dB over $3{\sim}5\;GHz$, and IIP3 of -21 dBm, while consuming 190 mW from a 1.8 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.895-902
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• 2014

This paper presents a 2-stage CMOS power amplifier for the 1.75 GHz band using a $0.18-{\mu}m$ CMOS process. Using ADS simulation, a power gain of 28 dB and an efficiency of 45 % at an 1dB compression point of 27 dBm were achieved. The implemented CMOS power amplifier delivered an output power of up to 24.8 dBm with a power-added efficiency of 41.3 % and a power gain of 22.9 dB. For a 16-QAM uplink LTE signal, the PA exhibited a power gain of 22.6 dB and an average output power of 23.1 dBm with a PAE of 35.1 % while meeting an ACLR(Adjacent Channel Leakage Ratio) level of -30 dBc.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.417-422
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• 2015

A 6.5 - 8.5 GHz CMOS UWB transmitter is implemented using $0.18{\mu}m$ CMOS technology. The transmitter is mainly composed of switched LC VCO and digital pulse generator (DPG). Using RF switch and DPG, the uniform power and sidelobe rejection are achieved irrespective of the carrier frequency. The measured UWB carrier frequency range is 7 ~ 8 GHz and the pulse width is tunable from 1 to 2 ns. The measured energy efficiency per pulse is 2.1 % and the power consumption is 0.6 mW at 10 Mbps without the buffer amplifier. The chip core size is $0.72mm^2$.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.1-8
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• 2013

This paper presents a variable gain amplifier(VGA) without passive devices. This VGA employes the architecture of current feedback amplifier and variable gain can be achieved by using the GM ratios of two trans-conductance(gm) circuits. To obtain linearity and high gain, it uses current division technique and source degeneration in feedback GM circuits. Input trans-conductance(GM) circuit was biased by using a tunable voltage controller to obtain variable gain. The prototype of the VGA is designed in $0.35{\mu}m$ CMOS technology and it is operating in sub-threshold region for low power consumption. The the gain of proposed VGA is varied from 23dB to 43dB, and current consumption is $2.82{\mu}A{\sim}3{\mu}A$ at 3.3V. The area of VGA is 1$120{\mu}m{\times}100{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.16-21
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• 2007

CMOS variable gain amplifier (VGA) IC designs for the structure monitoring systems of the telemetries were developed. A three stage cascaded VGA using a differential amplifier and a linear-in-dB controller is presented. A proposed VGA is a modified version of a conventional VGA such that the gain is controlled in a linear-in-dB fashion through the current ratio. The proposed VGA circuit introduced in this paper has a dynamic range of 77 dB with 1.5 dB gain steps. It also achieved a gain error of less than 1.5 dB over 77 dB gain range. The VGA can operate up to 10MHz dissipating 13.8 mW from a single 1.8 V supply. The core area of the VGA fabricated in a Magnachip $0.18{\mu}m$ standard CMOS process was about $430{\mu}m{\times}350{\mu}m$. According to measurement results, we can verify that the proposed method is reasonable with regard to the enhancement of dynamic range and the better linear-in-dB characteristics.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.531-532
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• 2008

In this paper, we present the comparison of the CMOS Double-Balanced Mixer for WLAN applications using the tail current source and not using it at the same current. The mixers are derived from the Gilbert cell mixer and have been simulated by using TSMC $0.18{\mu}m$ RF CMOS technology.