• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1753-1758
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• 2012

This paper introduces analog FIR filters based on a distributed amplifier and analyzes the proposed filter's characteristics. A simple design method of an analog FIR filter based on the digital filter design technique is also introduced. The proposed analog FIR filters are a moving average(MA) and a comb type filters with no multiplier. This simple structures of the proposed filters may enable to operate at multi-GHz frequency range and applicable to combine a filter and an amplifier of RF system. The proposed analog FIR filters were implemented with standard $0.18{\mu}m$ CMOS technology. The designed GHz analog FIR filters are simulated by Cadence Spectre and compared to the results of digital FIR filters obtained from MATLAB simulations. From the simulation results, the characteristics of the proposed analog FIR filters are fairly well matched with those of digital FIR filters.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.8-14
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• 2012

In this paper, a low-area FFT structure using $Radix-4^2$ algorithm is proposed. The large point FFT structure consists of cascade connection of the many stages. In implementation of large point FFT using $Radix-4^2$ algorithm, stages which number of different coefficients are only 3 appear in every 2 stages. For example, in the 4096-point FFT, the stages that number of different coefficients are 3 appear in stage 1, 3, and 5 among 6 stages. Multiplication block area of these 3 stages can be reduced using CSD(Canonic Signed Digit) and common sub-expression sharing techniques. Using the proposed structure, the 256-point FFT is implemented with the Verilog-HDL coding and synthesized by $1.971mm^2$ cell area in tsmc $0.18{\mu}m$CMOS library. This result shows 23% cell area reduction compared with the conventional structure.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.57-63
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• 2016

This paper describes implementation of the RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4g SUN sensor node transceiver modules. Design of the each module like VCO, prescaler, 1/N divider, ${\Delta}-{\Sigma}$ modulator, and common circuits of the PLL has been optimized to obtain high speed and low noise performance. Especially, the VCO has been designed with NP core structure and 13 steps cap-bank to get high speed, low noise, and wide band tuning range. The output frequencies of the implemented synthesizer is 1483MHz~2017MHz, the phase noise of the synthesizer is -98.63dBc/Hz at 100KHz offset and -122.05dBc/Hz at 1MHz offset.

• Journal of IKEEE
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• v.22 no.2
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• pp.393-401
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• 2018

In this paper, a rectifier for WPC / A4WP wireless power transmission is designed. The proposed rectifier supports both WPC (Wireless Power Consortium) and A4WP (Alliance For Wireless Power) and is designed with full-bridge rectifier. WPC transmits power at the frequency of 100kHz to 205kHz and A4WP at the frequency of 6.75MHz. Since the bridge rectifier uses a MOSFET instead of a diode, the reverse current flows and the efficiency is affected if the output voltage is higher than the input voltage. Therefore, we added the reverse current detector that detects the current flowing through the MOSFET and shut off the reverse current. The frequency discriminator is used because the rectifier has different frequency band. The proposed rectifier was designed using $0.35{\mu}m$ CMOS high voltage process. The input voltage is up to 18V and the rectifier operates at 100kH to 205kHz, 6.78MHz frequency. The maximum efficiency is 94.8% and the maximum power transfer is 5.78W.

• Journal of IKEEE
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• v.17 no.3
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• pp.234-240
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• 2013

This paper presents an incremental delta-sigma analog-to-digital converter (ADC) for a single-electrode capacitive touch sensor. The second-order cascade of integrators with distributed feedback (CIFB) delta-sigma modulator with 1-bit quantization was fabricated by a $0.18-{\mu}m$ CMOS process. In order to achieve a wide input range in this incremental delta-sigma analog-to-digital converter, the shielding signal and the digitally controlled offset capacitors are used in front of a converter. This circuit operated at a supply voltage of 2.6 V to 3.7 V, and is suitable for single-electrode capacitive touch sensor for ${\pm}10-pF$ input range with sub-fF resolution.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.36-44
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• 2015

This paper proposes a low-complexity processor to correct vignetting and barrel distortion for wide-angle cameras. The proposed processor calculates the required correcting factors by employing the piecewise linear approximation so that the hardware complexity can be reduced significantly while maintaining correction quality. In addition, the processor is designed to correct the two distortions concurrently in a singular pipeline, which reduces the overall complexity. The proposed processor is implemented with 18.6K logic gates in a $0.11{\mu}m$ CMOS process and shows the maximum correction speed of 200Mpixels/s for correcting an image of which size is $2048{\times}2048$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.893-898
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• 2017

A TDC(Time-to-Digital Converter) of counter-type is designed by $0.18{\mu}mCMOS$process and the supply voltage is 1.5 volts. The converted error of maximum $T_{CK}$ is occurred by the time difference between the start signal and the clock when the period of clock is $T_{CK}$ in the conventional TDC. And the converted error of -$T_{CK}$ is occurred by the time difference between the stop signal and the clock. However in order to compensate the disadvantage of the conventional TDC the clock is generated within the TDC circuit and the clock is synchronized with the start and stop signals. In the designed TDC circuit the conversion error is not occurred by the difference between the start signal and the click and the magnitude of conversion error is reduced (1/2)$T_{CK}$ by the time difference between the stop signal and the clock.

• Journal of Sensor Science and Technology
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• v.12 no.4
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• pp.191-197
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• 2003

Due to explosive increase of internet usage, broadband data transmission using optical fibers is broadly used. In order to decrease distortion during long distance transmission, the optical signal need to be restored, typically, by converting the optical signal into the electrical signal. The optical signal is converted into the electrical signal using a photo-diode, and then a clock-and-recovery (CDR) circuit is used to recover the clock and retime the data. In this study, a clock-and-data recovery circuit has been designed using a standard 1.8 V $0.18\;{\mu}m$ CMOS process. With this CDR circuit, the improved phase detector and charge pump have been utilized. Also, by using a ring oscillator, the CDR circuit can recover clock and data from broadband multi-rate data ranging between 750 Mb/s and 2.85 Gb/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.