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Code Rate 1/2, 2304-b LDPC Decoder for IEEE 802.16e WiMAX

IEEE 802.16e WiMAX용 부호율 1/2, 2304-비트 LDPC 복호기

  • Received : 2010.12.08
  • Accepted : 2011.03.31
  • Published : 2011.04.30

Abstract

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

모바일 WiMAX 표준 IEEE 802.16e의 블록길이 2,304 비트, 부호율 1/2을 지원하는 LDPC(low-density parity-check) 복호기를 설계하였다. 설계된 LDPC 복호기는 최소-합(min-sum) 알고리듬과 layered 복호를 기반으로 $96{\times}96$ 크기의 부행렬을 병렬로 처리하는 부분병렬 구조를 갖는다. 최소-합 알고리듬의 특징을 이용하여 메모리 용량을 감소시킬 수 있는 새로운 방법을 고안하여 적용함으로써 검사노드 메모리 용량을 기존의 방법보다 46% 감소시켰다. Verilog HDL로 설계된 LDPC 복호기를 $0.18{\mu}m$ CMOS 셀 라이브러리로 합성한 결과 174,181개의 게이트와 52,992 비프의 메모리로 구현되었으며, Eb/No=2.1dB의 AWGN 채널에 대해 평균 비트 오율 (BER)는 $4.34{\times}10^{-5}$이고, 100 MHz@1.8-V로 동작하여 약 417 Mbps의 성능을 갖는다.

Keywords

References

  1. R.G. Gallager, Low-Density Parity-Check Codes, Cambridge, MA: MIT Press, 1963.
  2. D. Mackay, "Good error correcting codes based on very sparse matrices," IEEE Trans. Information Theory, Vol.45, No.3, pp.399-431, Mar., 1999. https://doi.org/10.1109/18.748992
  3. T.J. Rhicardson and R. Urbanke, "Efficient Encoding of Low-Density Parity-Check Codes," IEEE Trans. Information Theory, Vol.47, No.2, pp.638-656, Feb., 2001. https://doi.org/10.1109/18.910579
  4. DVB-S2 Draft ETSI EN 302 307 V1.1.1 (2004- 06), ETSI
  5. IEEE P802.11n/D3.07, Wireless LAN Medium Access Control(MAC) and Physical Layer (PHY) specifications: Enhancements for Higher Through- put, IEEE Std. 802.11n, 2008.
  6. IEEE Standard for Local and metropolitan area networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems Amendment 2: Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands and Corrigendum 1, IEEE Std. 802.16e, 2005.
  7. IEEE Standard for Information Technology Telecommunications and Information Exchange Between Systems Local and Metropolitan Area Networks - Specific Requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer and Management Parameters for 10 Gb/s Operation Type 10GBASE-T, IEEE Std 802.2an, 2006.
  8. R.M. Tanner, "A recursive approach to low complexity codes," IEEE Trans. Inform. Theory, Vol.27, No.5, pp.533-547, Sep., 1981. https://doi.org/10.1109/TIT.1981.1056404
  9. M.M. Mansour and N.R. Shanbhag, "High Throughput LDPC Decoders," IEEE Trans. Very Large Scale Integration(VLSI) Systems, Vol.11, No.6, pp.976-996, Dec., 2003. https://doi.org/10.1109/TVLSI.2003.817545
  10. W.E. Ryan, "An Introduction to LDPC Codes," in CRC Handbook for Coding and Signal Processing for Recoding Systems (B. Vasic, ed.), CRC Press, 2004.
  11. X.Y. Shih, C.Z. Zhan, C.H. Lin and A.Y. Wu, "An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 um CMOS Process," IEEE Journal of Solid-State Circuits, Vol.43, No.3, pp.672-683, Mar., 2008. https://doi.org/10.1109/JSSC.2008.916606
  12. C.H. Liu, S.W. Yen, C.L. Chen, H.C. Chang, C.Y. Lee, Y.S. Hsu and S.J. Jou, "An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications," IEEE Journal of Solid-State Circuits, Vol.43, No.3, pp.684-694, Mar., 2008. https://doi.org/10.1109/JSSC.2007.916610
  13. T.C. Kuo and A.N. Willson, Jr., "A Flexible Decoder IC for WiMAX QC-LDPC Codes," Proc. of IEEE Custom Integrated Circuits Conf. (CICC), pp.527-530, 2008.
  14. J. Sha, M. Gao, Z. Zhang, L. Li and Z. Wang, "An FPGA Implementation of Array LDPC Decoder", Proc. of IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS), pp.1675-1678, 2006.
  15. C. Zhang, Z. Wang, J. Sha, L. Li and J. Lin, "Flexible LDPC Decoder Design for Multi-giga bit-per-Second Applications", IEEE Trans. on Circuits and Systems I, Vol.57, No.1, pp.116-124, Jan., 2010 https://doi.org/10.1109/TCSI.2009.2018915
  16. K. He, J. Sha, L. Li, Z. Wang, "Low power decoder design for QC-LDPC codes", Proc. of 2010 IEEE Int. Symp. on Circuits and Systems (ISCAS), pp.3937-3940, 2010.