• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.504-512
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• 2010

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.7
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• pp.1254-1259
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• 2008

A new CMOS current-mode integrator for low-voltage analog integrated circuit design is presented. The proposed current-mode integrator is based on cross-coupled gain-boosting topology. When it is compared with that of the typical current-mirror type current-mode integrator, the proposed current-mode integrator achieves high current gain and unity gain frequency with the same transistor size. As a application circuit of the proposed integrator, we designed the 1.8V 200MHz band current-mode lowpass filter. These are verified by Hspice simulation using $0.18{\mu}m$ CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.19-29
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• 2002

A simple and analytical design approach for input power matched CMOS RF LNA circuits and their scaling for lower power consumption, is introduced. In spite of the simplicity of our expressions, it gives excellent agreement with numerical simulation results using commercial CAD tools for several circuit examples performed at 2.4GHz using $0.18\mu\textrm{m}$ CMOS technology. These simple and analytical results are extremely useful in that they can provide enough insights not only for designing any CMOS LNA circuits, but also for characterizing and diagnosing them whether being prototyped or manufactured.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.62-66
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• 2016

This paper presents a MedRadio-band low power low noise amplifier for Medical Devices. A proposed MedRadio-band low power low noise amplifier adopts a current-reuse resistive feedback topology to increase overall gm and reduce power consumption. The gain of the LNA increases by the Q-factor of the additional series RLC input matching network, and its noise figure is minimized by the similar factor. Furthermore, it consumes low power because of low supply voltage and current reuse technique. By exploiting the $g_m$-booting and matching network property, the proposed MedRadio-band low noise amplifier achieves a noise figure of 0.85 dB, a voltage gain of 30 dB, and IIP3 of -7.9 dBm while consuming 0.18 mA from a 1 V supply voltage in $0.13{\mu}m$ CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.73-81
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• 2012

In this paper, a novel phase locked loop has been proposed using an analog band-selection loop. When the PLL is out-lock, the PLL has a fasting locking characteristic with the analog band-selection loop. When the PLL is near in-lock, the bandwidth becomes narrow with the fine loop. A frequency voltage converter is introduced to improve a stability and a phase noise performance. The proposed PLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of IKEEE
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• v.18 no.3
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• pp.320-327
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• 2014

Recently, Importance of power management circuit technology is increased with the development of portable electric devices. This paper presents a high performance DC-DC buck converter for mobile applications. Especially, presented design have low ripple voltages and driving capability of large load current. A designed voltage mode 2-phase DC-DC converter is implemented in a $0.35{\mu}m$ CMOS process, and the overall size is $2.35{\times}2.35mm^2$. The peak efficiency is 91% with a 4MHz frequency and the maximum load current is 4A.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2380-2386
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• 2013

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and 2nd-order RC filter has been proposed. The goal of the proposed PLL is the suppression of reference spur which is caused by charge pump mismatch. It also improves phase noise characteristic. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.47-52
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• 2010

In this paper, a phase-locked loop with a self-noise suppressing voltage controlled oscillator to improve a phase noise characteristic has been proposed. The magnitude of the proposed transfer function is maximum 25dB lower than that of a conventional transfer function around a bandwidth. The proposed PLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.125-136
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• 2009

This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.