• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.7-12
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• 2007

A SPICE-based 3-dimensional circuit model of LED(Light-Emitting Diode) was developed for the design optimization and analysis of high-brightness LEDs. An LED is represented as an array of pixel LEDs with small preassigned areas, and each of the pixel LEDs is composed of circuit networks representing the thin-film layers(n-metal, n- and p-type semiconductor layers, and p-metal), ohmic contacts, and pn-junctions. Each of the thin-film layers and contact resistances is modeled by a resistance network, and the pn-junction is modeled by a conventional pn-junction diode. It has been found that the simulation results using the model and the corresponding parameters precisely fit the measured LED characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.231-231
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• 2011

바늘침 전극을 사용한 대기압 플라즈마 제트의 전기적 특성을 조사하였다. 접지 전극 위치, 안정 커패시터 크기 등 변수에 따라서 플라즈마 제트 방전 특성의 변화를 조사한다. 각 실험조건의 등가회로를 통해서, 플라즈마 방전 특성(IV-curve)을 분석한다. 등가회로에서 안정 커패시터 Cp, 유리관 내부 플라즈마 저항 RP, 접지측 유리층 커패시턴스 CG, 대기 접지 RA, 등의 각 변수들을 검토한다. Rp 및 Rj는 방전이 강해질수록 작아진다. 특히 타운젠트 방전 후 Rp 및 Rj는 약 수십 $k{\Omega}$으로 작아진다, 회로 전체 임피던스와 비교하면 아주 작은 값이다. 안정 커패시터 와 접지 측 유리 층의 임피던스는 수백 $k{\Omega}$으로 아주 크다. 방전이 진행되면서 플라즈마 저항 Rp 및 Rj가 급감하여도 Cp 및 CG의 역할로 회로전체 임피던스가 일정한 값을 유지할 수 있어서 전류가 급증 하는 것을 방지할 수 있다. 대기 접지 RA는 $M{\Omega}$으로, 접지 전극이 없을 때 방전 개시전압도 높아진다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.436-439
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• 2011

본 논문은 클록 보정회로를 가진 1V 2.56-GS/s 6-bit flash analog-to-digital converter (ADC) 제안한다. 제안하는 ADC 구조에서 아날로그 블록은 단일 T/H와 2단의 프리앰프, 그리고 비교기를 사용된다. 2단의 프리앰프와 비교기의 출력에 옵셋의 크기를 줄이기 위하여 저항 평균화 기법을 적용하였다. 디지털 블록은 quasi-gray rom base 구조를 사용한다. 3입력 voting 회로로 flash ADC에서 발생하기 쉬운 bubble error를 제거하였으며, 고속 동작을 위해 단일 클록을 사용하는 TSPC F/F로 구현한다. 제안하는 flash ADC는 클록 듀티 비를 조절할 수 있는 클록 보정회로를 사용한다. 클록 보정 회로는 비교기 클록 듀티 비를 조절하여 리셋 시간과 evaluation 시간의 비율을 최적화함으로 dynamic 특성을 확보한다. 제안한 flash ADC는 1V 90nm의 CMOS 공정에서 설계되었다. Full power bandwidth인 1.2 GHz 입력에 대하여 ADC 성능을 시뮬레이션을 통해 확인하였다. 설계된 flash ADC의 면적과 전력소모는 각각 $800{\times}400\;{\mu}m^2$와 193.02mW 이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.3
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• pp.531-536
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• 2009

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure around the unit pixel. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.1-12
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• 2001

The adaptive learning circuit is designed on the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results are analyzed. The output frequency of the adaptive learning circuit is inversely proportional to the source-drain resistance of MFSFET and the capacitance of the circuit. The saturated drain current with input pulse number is analogous to the ferroelectric polarization reversal. It indicates that the ferroelectric polarization plays an important role in the drain current control of MFSFET. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of input pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, the frequency modulation characteristic of the adaptive learning circuit are confirmed. In other words, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse are confirmed. Consequently it is shown that our circuit can be used effectively in the neuron synapses of nueral networks.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.2
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• pp.1051-1058
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• 2014

This paper presents a Electrical characteristics of the Memristor device using the PSPICE for circuit analysis. After making macro model of the Memristor device for circuit analysis, electric characteristics of the model such as time analysis, frequency and DC analysis according to the input voltage were performed by PSPICE simulation. Also, we made simple circuits of memristor series and parallel structure and analyzed the simulated SPICE results. Finally, we made a memristor-capacitor (M-C) circuit. charge and discharge characteristics were analyzed. In case of input pulse signal of 250 Hz, the Memristor-capacitor circuit showed delay time of 0.6ms, rising time of 0.58 ms and falling time of 1.6 ms.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.6
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• pp.1-5
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• 1977

The input equivalent resistances and operating properties of a transless double balanced modulator are quantitatively investigated in considerations of the nonlinear characteristics of diodes. The input equivalent resistances are derived from the power loss calculations of the circuit. Carrier suppression and modulation efficiency are calculated by using approximate equations which describe the dynamic curves of the diode circuits. The results are represented as a function of the voltage amplitude of a carrier signal owing to the nonlinear characteristics of diodes.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.72-76
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• 2003

The defected ground structure (DGS ) for microstrip structure can be used to protect analog/RF signal from SSN interference of digital circuits on PCB with common ground. However, the basic DGS gives rise to undesired emissions that may interfere with nearby circuitry due to the ground discontinuity. In this paper, we have proposed the modified structure, Corrugated DGS and the method to reduce the radiation by adding the lumped resistor on the proposed Corrugated DGS.

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.7-13
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• 2001

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently. IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. This paper presents a new BIC for the internal current test in CMOS logic circuit. Our circuit is composed of Magnetoresistive current sensor, level shifter, comparator, reference voltage circuit and a circuit be IDDQ tested as a kind of self-testing fashion by using the proposed BIC.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.157-158
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• 2012

본 논문은 리튬 폴리머 배터리의 수명 감소에 대한 경향성 테스트를 토대로 이중 확장 칼만 필터(Dual EKF)를 이용하여 배터리의 SOC(State-of-Charge) 및 SOH(State-of-Charge) 방법을 제안하였다. 배터리에 수명에 따른 임피던스 변화를 테스트를 수행함으로써 등가회로 모델상에서 수명에 따른 변화가 가장 큰 내부 저항을 선택함으로써 배터리의 SOH 추정을 위해 선택하였다. 배터리 모델은 4.2V, 1440mAh의 리튬폴리머 전지에서 추출되었다. 배터리는 Bulk 커패시터, 두 개의 R-C회로, 직렬 저항을 사용하여 모델링하였다. Dual EKF를 모델에 적용하기 위해 캐패시터 전압은 개방 회로 전압(OCV)을 나타내는데 사용된다. Dual EKF는 충/방전 기기인 TOSCAT-5200에 의해 얻은 실험 데이터로 테스트하였다.