• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.9 no.2
• /
• pp.51-59
• /
• 2010

In this paper, we propose an inverted type asymmetric Doherty amplifier with optimized efficiency characteristic in wanted output power back-off (OPBO) range according to peak to average power ratio of input signal In order to obtain optimized efficiency of the asymmetric Doherty amplifier in wanted OPBO, peak power ratio between main amplifier and peaking amplifier was determined and then impedance of 90 degrees impedance transformer was obtained by peak power ratio. The offset line length and peak dividing ratio of the asymmetric Doherty amplifier were also calculated. From the measurement results, the proposed amplifier has achieved 40 % drain efficiency and -35 dBc adjacent channel leakage ratio at the average output power of 48.7 dBm for CDMA 2000 1x 3-FA test signal.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.1
• /
• pp.33-38
• /
• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.

• 한국방재학회:학술대회논문집
• /
• 2007.02a
• /
• pp.137-139
• /
• 2007

To enhance capability on discerning local and regional seismic phases, such as, Pn, Pg, Sn, Rg, etc, within the crust, 2-D numerical forward modeling will be applied to the data obtained from local seismic stations by simulating almost all waves including not only body wave but also surface wave generated without having to explicitly include them under consideration of Q factor. In this study, after getting rid of instrumental response by deconvolution, pseudo-spectral method instead of relying on typical numerical methods, such as, FEM(Finite Element Method) and FDM(Finite Difference Method), will be implemented for 2-D numerical forward modeling by considering velocities of P-wave and S-wave, density, and Q factors. Ultimately, the Power of reaching the enhanced capability on discerning local and regional seismic phases will make it easier for us to identify the seismic source, whether it is originated from man-made explosion or pure earthquake.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.17 no.6 s.109
• /
• pp.538-545
• /
• 2006

In this paper, an asymmetric high power extended Doherty amplifier for WCDMA base-station applications is presented. The amplifier has an extended peak efficiency over 9 dB of output power and a linear dynamic range characteristic. To realize the peak efficiency extension and linear dynamic range characteristic, a two times larger peaking device compared to the main device, and an unequal power divider are used. From the experimental results of 1FA WCDMA signal, this amplifier has an efficiency of 31 % and an ACLR of -35 dBc is achieved at 9 dB back-off from P1 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.9
• /
• pp.900-905
• /
• 2009

A common drain feedback CMOS wideband LNA with current bleeding and input inductive series-peaking techniques is presented in this paper. DC coupling is adopted between cascode and feedback amplifiers, so that the gain and NF of the LNA can be dynamically controlled by adjusting the bleeding current. The fabricated LNA shows the bandwidth of 2.5 GHz. The high gain mode shows 17.5 dB gain with $1.7{\sim}2.8\;dB$ NF and consumes 27 mW power and the low gain mode has 14 dB gain with $2.7{\sim}4.0\;dB$ NF and dissipates 1.8 mW from 1.8 V supply.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.39B no.7
• /
• pp.440-448
• /
• 2014

A $4{\times}10$ Gb/s Transimpedance Amplifier (TIA) array is implemented in $0.13{\mu}m$ CMOS process technology, which will be used in the receiver of TWDM-PON system. A technology for bandwidth enhancement of a given $4{\times}10$ Gb/s TIA presented under inductor peaking technology and a single 1.2V power supply based low voltage design technology. It achieves 3 dB bandwidth of 7 GHz in the presence of a 0.5 pF photodiode capacitance. The trans-resistance gain is $50dB{\Omega}$, while 48 mW/ 1channel from a 1.2 V supply. The input sensitivity of the TIA is -27 dBm. The chip size is $1.9mm{\times}2.2mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.8 s.338
• /
• pp.53-60
• /
• 2005

Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.3
• /
• pp.34-38
• /
• 2000

This paper describes design, fabrication, and performance of an ultra-high-speed and low-noise MMIC (Monolithic Microwave Integrated Circuit) preamplifier for a 10 Gb/s optical receiver. The transimpedance type 3-stage MMIC preamplifier for ultra-high-speed and low-noise was designed using an AlGaAs/InGaAs/GaAs P-HEMTs(Pseudomorphic High Electron Mobility Transistors) with 0.15${\mu}{\textrm}{m}$ length T-shaped gate. To obtain broadband characteristics, we used the inductor peaking technique, and the gate width was optimized for low noise performance. Measurements reveal that the fabricated preamplifier has the high transimpedance gain of 60 ㏈Ω and 9.15 ㎓ bandwidth with the noise figure of less than 3.9 ㏈.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.8
• /
• pp.717-724
• /
• 2016

This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and low-power consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.12
• /
• pp.71-79
• /
• 2013

This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver adapts to channel and chip process variation by adaptation circuit using sampler and serializer. The adaptation principle is explained. It describes technique receiving ground referenced differential signal of voltage-mode transmitter for low-power. The CTLE(Continuous Time Linear Equalizer) having 17.6 dB peaking gain to remove long tail ISI caused channel with -21 dB attenuation. The voltage margin is 210 mV and the timing margin is 0.75 UI in eye diagram. The receiver consumes 0.87 mW/Gb/s low power in 45 nm CMOS technology.