Browse > Article
http://dx.doi.org/10.7840/kics.2014.39B.7.440

A Design and Implementation of 4×10 Gb/s Transimpedance Amplifiers (TIA) Array for TWDM-PON  

Yang, Choong-Reol (ETRI Optical Internet Research Department Optical Access Laboratory)
Lee, Kang-Yoon (SungKyunKwan University Electric & Electronics Engineering Department)
Lee, Sang-Soo (ETRI Optical Internet Research Department Optical Access Laboratory)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.39B, no.7, 2014 , pp. 440-448 More about this Journal
Abstract
A $4{\times}10$ Gb/s Transimpedance Amplifier (TIA) array is implemented in $0.13{\mu}m$ CMOS process technology, which will be used in the receiver of TWDM-PON system. A technology for bandwidth enhancement of a given $4{\times}10$ Gb/s TIA presented under inductor peaking technology and a single 1.2V power supply based low voltage design technology. It achieves 3 dB bandwidth of 7 GHz in the presence of a 0.5 pF photodiode capacitance. The trans-resistance gain is $50dB{\Omega}$, while 48 mW/ 1channel from a 1.2 V supply. The input sensitivity of the TIA is -27 dBm. The chip size is $1.9mm{\times}2.2mm$.
Keywords
TWDM-PON; Optical Transceiver; CMOS; Transimpedance Amplifier; TIA; Array;
Citations & Related Records
연도 인용수 순위
  • Reference
1 T. Takemoto, H. Yamashita, T. Yazaki, N. Chujo, Y. Lee, and Y. Matsuoka, "A 4${\times}$ 25-to-28Gb/s 4.9mW/Gb/s −9.7dBm highsensitivity optical receiver based on 65nm CMOS for board-to-board interconnects," IEEE Int. ISSCC, pp. 118-119, San Francisco, CA, Feb. 2013.
2 Company: Commercial PD (BPD2010-12_Cosemi).
3 Y. Chen, et al., "0.0012, 8mW, single-todifferential converter with < 1.1% data cross error and < 3.4 ps RMS jitter up to 14 Gbit/s data rate," IET ELECTRONICS Lett., vol. 49, no. 11, pp. 692-694, May 2013.   DOI
4 X. Zhang, et al., "Design of lower power 4x10Gb/s VCSEL driver array," IEEE MTT-S Int. Microwave Workshop Series on Millimeter Wave Wirel. Technol. Appl. (IMWS), pp. 1-3, Sept. 2012.
5 Y.-T. Lin, et al., "A Low-Variation, Low- Voltage CMOS Bandgap Reference Circuit," Dept. of Electronic Eng., Lunghwa Univ. of Science and Technol., Issue 25, Jun. 2008.
6 T. D. Ridder, et al., "A 2.7V 9.8Gb/s burst-mode TIA with fast automatic gain locking and coarse threshold extraction," IEEE Int. ISSCC, pp. 220-221, San Francisco, CA, Feb. 2008.
7 T.-H. N해, T.-W. Lee, and H.-H. Park, "Design of transimpedance amplifier for optical receivers in 0.13 ${\mu}m$ CMOS," Int. Conf. Optical Internet (COIN), pp. 1-3, Jeju, Korea, Jul. 2010.
8 X. Yin, et al., "A 10Gb/s burst-mode TIA with on-chip reset/lock CM signaling detection and limiting amplifier with a 75ns Settling Time," IEEE Int. ISSCC, pp. 416-418, San Francisco, CA, Feb. 2012.
9 D.-U. Li and H.-C. Chen, "10Gb/s 0.13${\mu}m$ CMOS laser drivers with extinction ratio control using thermistors," Solid State Circuits Conf. (ESSCIRC 2007), pp. 260-263, Munich, Sept. 2007.
10 E. Hammoudi, B. Imad, and D. Mohamed, "High bandwidth 0.35${\mu}m$ CMOS transimpedance amplifier," Int. Conf. Complex Systems (ICCS), Digital Object Identifier, pp. 1-6, 2012.