• The KIPS Transactions:PartB
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• v.10B no.2
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• pp.143-150
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• 2003

Error concealment plays an important role in combating transmission errors. Methods of error concealment which produce better quality are generally of higher complexity, thus making some of the more sophisticated algorithms is not suitable for real-time applications. In this paper, we develop temporal and spatial error resilient video encoding and data hiding approach to facilitate the error concealment at the decoder. Block interleaving scheme is introduced to isolate erroneous blocks caused by packet losses for spatial area of error resilience. For temporal area of error resilience, data hiding is applied to the transmission of parity bits to protect motion vectors. To do error concealment quickly, a set of edge features extracted from a block is embedded imperceptibly using data hiding into the host media and transmitted to decoder. If some part of the media data is damaged during transmission, the embedded features are used for concealment of lost data at decoder. This method decreases a complexity of error concealment by reducing the estimation process of lost data from neighbor blocks. The proposed data hiding method of parity bits and block features is not influence much to the complexity of standard encoder. Experimental results show that proposed method conceals properly and effectively burst errors occurred on transmission channel like Internet.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.11
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• pp.19-23
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• 2010

In this paper, we propose a combining scheme for partial IR based hybrid ARQ in MIMO systems. The proposed combining scheme is a symbol-level combining scheme for repeatedly transmitted systematic symbols in partial IR based hybrid ARQ. In this paper, it is shown that the proposed combining scheme can also enhance the detection performance of the parity symbols that are newly transmitted in each retransmission. Simulation results show that the proposed combining scheme significantly improves the performance of the partial IR based hybrid ARQ compared to the cases of the conventional bit-level combining scheme, especially with the ZF detection.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2207-2214
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• 2010

Underwater acoustic(UWA) communication has multipath error because of reflection by sea-level and sea-bottom. The multipath of UWA channel causes signal distortion and error floor. In this paper, we proposed split input bits of channel decoder using method of maximum value, average value, LLR value for optimal estimation. Channel coding method is LDPC(N size=16000) standard in DVB-S2. As shown in simulation results, the performance of LLR value method is better than other methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.8C
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• pp.522-528
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• 2011

The iterative detection and decoding (IDD) has been shown to dramatically improve the bit error rate (BER) performance of the multiple-input multiple-output (MIMO) communication systems. However, these techniques require a high computational complexity since it is required to compute the soft decisions for each bit. In this paper, we show IDD comprised of sphere decoder with low-density parity check (LDPC) codes and present the tree search strategy, called a layer symbol search (LSS), to obtain soft decisions with a low computational complexity. In addition, an adaptive early termination is proposed to reduce the computational complexity during an iteration between an inner sphere decoder and an outer LDPC decoder. It is shown that the proposed approach can achieve the performance similar to an existing algorithm with 70% lower computational complexity compared to the conventional algorithms.

• The Journal of the Korea Contents Association
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• v.12 no.12
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• pp.14-24
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• 2012

DVC (Distributed Video Coding) techniques need feedback channel for parity bit control to achieve the good RD performances, however, this causes the DVC system to have high decoding latency. In order to implement in real time environments and to accelerate commercializations, many research works have been focusing on the development of fast video decoding algorithm. As one of the real time implementations, this paper deals with a novel DVC scheme suitable for some application areas where source statistics such as motion information can be provided to the encoder side from the decoder side. That is, this paper propose a fast distributed video decoding scheme to improve the decoding speed by using the feedback of motion information derived in SI generation. Through computer simulations, it is shown that the proposed method outperforms the conventional fast DVC decoding schemes.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.2
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• pp.53-64
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• 2011

In this paper, we propose a channel estimation of side information method based received motion vectors for distributed video coding. The proposed decoder estimates motion vectors of side information and transmits it to the encoder. As the proposed encoder generates side information which is the same to one in the decoder with received motion vectors, accuracy of side information of the decoder is assessed and it is transmitted to decoder. The proposed decoder can also estimate accurate crossover probability with received error information. As the proposed method conducts correct belief propagation, computational complexity of the channel decoder decreases and error correction capability is significantly improved with the smaller amount of parity bits. Experimental results show that the proposed algorithm is better in rate-distortion performance and it is faster than several conventional distributed video coding methods.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1948-1959
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• 1999

The error rate performance of the proposed $\pi$/4-differential quadructure phase shift keying( $\pi$/4-DQPSK) with nonredundant multiple error correction is analyzed for Nakagami fading channel. The scheme for differential detection of $\pi$/4-QPSK with nonredundant multiple error correction utilizes the output that employ the received signal delayed by more than two time slots. It was observed that the performance increased as the error correction capability increased.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.939-947
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• 2010

The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1107-1114
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• 2004

System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.