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A new design method of m-bit parallel BCH encoder  

Lee, June (LG전자 D&S 연구소)
Woo, Choong-Chae (한서대학교 컴퓨터공학과)
Publication Information
Journal of the Institute of Convergence Signal Processing / v.11, no.3, 2010 , pp. 244-249 More about this Journal
Abstract
The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.
Keywords
Parallel BCH encoder; sub-expression; error correction code;
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