1 |
X. Zhang and K. K. Parhi, "High-speed architecture for parallel long BCH encoders," IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 13, no. 7, pp. 872-877, July 2005.
DOI
|
2 |
K. K. Parhi, "Eliminating the Fanout Bottleneck in Parallel Long BCH Encoders," IEEE Tran. on Circuits and Systems, vol. 51, no. 3, pp. 512-516, Mar. 2004.
DOI
ScienceOn
|
3 |
S. B. Wicker, "Error Control Systems for Digital Communication and Storage," Prentice Hall, Upper addle River, New Jersey, 1995.
|
4 |
W. Liu, J. Rho, and W. Sung, "Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories," in Proc. Int. Workshop SiPS, pp. 248 - 253, 2006.
|
5 |
X. Wang et aI., "A high-speed two-cell BCH decoder for error correnting in MLC NOR flash memories,", IEEE Transaction on Circuit and Systems ll: Express Briefs, vol. 56, no. 11, pp 865-869, 2009.
DOI
|
6 |
S. Lin and D. J. Costello, Error control coding: Fundamentals and application (second edition), Prentice Hall, 2004.
|
7 |
J. Zhang, Z. Wang, Q. Hu, and J. Xiao, "Optimized design for highspeed parallel BCH encoder," in Proc. IEEE Int. Workshop. VLSI Des. & Video Tech., pp. 97 - 100, May 2005.
|