• Journal of the Korean Institute of Gas
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• v.18 no.5
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• pp.26-32
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• 2014

CCS(Carbon Capture and Storage) which is technic to capture and storage the carbon-dioxide is the method that reduces the carbon-dioxide from the industries to prevent earth from the global warming. In order to apply to the practical site, it is inevitable to investigate the possibility of damage in the pipe or components by carbon-dioxide. In this paper, the immersion test is performed to estimate the suitability of the rubber which is used to seal or connect the pipelines because the rubber has not been validated. Also, the immersion test is carried out in a certain condition(pre- and supercritical state).

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.5
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• pp.3-11
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• 2005

This paper presents a performance analysis model based on an M/M/1 queue and Poisson distribution of input data traffic. The simulation on a pipelined AES system with processing rate of 10 rounds per clock shows $4.0\%$ higher performance than a non-pipelined version consuming 10 clocks per transaction. Physical implementation of pipelined AES with FPGA takes 3.5 times bigger gate counts than the non-pipelined version whereas the pipelined version yields only $3.5\%$ performance enhancement. The proposed analysis model can be used to optimize cost-performance of AES hardware designs.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.06a
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• pp.315-316
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• 2022

In order to reduce maritime accidents and promote maritime safety and the happiness of the sea people, the Ministry of Oceans and Fisheries has been providing Intelligent Maritime Traffic Information services to the public from the end of January 2021. Various information is generated and collected through this service, and research and development is underway to develop and verify a service algorithm by applying the collected information to data science to realize a safer and more efficient intelligent maritime traffic information service. In order to develop and implement this, a data pipeline system that connects the collected and stored data and can access, use, and store data from multiple systems smoothly is required. Therefore, in this study, a data pipeline that can be used in various systems such as a datascience based service algorithm development environment and an intelligent maritime transportation service test-bed was designed.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.826-828
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• 2005

인텔의 IA-64 프로세서는 명령어 수준의 병렬수행을 지원하는 EPIC (Explicitly Parallel Instruction Computing) 구조를 채택하고 있으며 컴파일러가 순차적 코드에서 병렬 수행이 가능한 독립적인 명령어들을 스케줄링 하도록 되어있다. 본 논문에서는 IA-64 스케줄링을 위해 향상된 파이프라인 스케줄링 (Enhanced Pipeline Scheduling, EPS) 기법[1]을 적용한 결과를 소개한다. EPS는 루프수준의 병렬화를 위한 소프트웨어 파이프라이닝 (software pipelining)기법으로 전역 스케줄링 (global Scheduling) 기법을 기반으로 하고 있다. 우리는 IA-64 프로세서를 위한 공개소스 컴파일러인 ORC (Open Research Compiler)에 EPS를 구현하고 실제 프로세서인 Itanium에서 실험을 수행하였다. 상용 프로세서와 컴파일러에 구현과 튜닝을 하는 과정에서 얻은 경험을 소개하고 기존의 ORC 컴파일러와 비교하여 얻은 성능 향상을 보고하고 분석한다.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• v.10 no.2
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• pp.32-35
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• 2005

밭고랑 옆의 해가림시설 지주목에 파이프라인을 설치하고 방제장치를 탑재한 주행장치가 자동으로 파이프를 추적하면서 농약을 살포 할 수 있는 방제기를 개발하여 인삼재배포장에서 성능시험을 실시하였다. 그 결과를 요약하면다음과 같다. 가. 인삼재배용 방제기의 주행장치는 동력원으로 축전지를 사용하는 DC모터에 의한 4륜 구동형으로 제작하였고, 방제장치는 수직 붐노즐 방식으로 쌍선형 노즐을 좌우에 3개씩 부착하고 살포각도를 조절할 수 있도록 제작하였으며, 인력으로 골간 이동시키는 방식이다 나. 성능시험결과 주행속도는 0.3m/s이고, 장애물이나 요철부의 통과 가능높이는 4cm였고, 작업성능은 38분/10a로 나타났다. 다. 방제성능은 피복면적비를 측정한 결과 인삼 잎 앞면은 100%, 뒷면은 40%이상으로 분무입자의 부착률이 양호한 것으로 나타났다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.788-795
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• 2000

Scattered look-ahead pipelining method can be efficiently used for high sample rate or low-power applications of digital recursive filters. Although the pipelined filters are guaranteed to be stable by this method, these filters suffer from large round off noise when the poles are crowed within some critical regions. To avoid this problem, a low-noise implementation technique was proposed using constrained Remez exchange algorithm. By the constrained filter design approach, the desired filter spectrum is satisfied while some of the pole angles are constrained to avoid pole crowding within critical regions. In the proposed approach, to obtain improved spectrum characteristics or better round off noise properties, the radius of the angle-constrained pole is optimized depending on the direction of the pole movement.

• Journal of Digital Contents Society
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• v.12 no.4
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• pp.491-499
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• 2011

Though there has been great advances in films' computer graphics both in technical and artistic side, there is still a big gap between computer graphics (a.k.a CG) studios in South Korea and major CG studios in US. Therefore, in this research, based on working experience at Disney Animation and information from working professionals in major CG studios, this paper analyzes strengths and weakness of character pipeline that major CG studios have by using examples and then suggest what CG studios in South Korea need. Steps of research process is to analyze what CG studios in South Korea developed, what are the strengths and weakness of Disney's character pipeline system and how these strengths can be applied to CG studios in South Korea.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.125-136
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• 2009

This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.1
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• pp.104-110
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• 2009

In this paper, we suggest a new technique which employ the pipelined architecture for the implementation of the SAP adaptive filter using variable step size. According as SAP adaptive filter is sufficiently decomposed, a simplified SAP adaptive filter can be derived, and the weights of adaptive sub-filters can be updated by a simple formular without a matrix inversion. The convergence speed and the steady state error of the simplified SAP adaptive filter are improved by using variable step size. For practical implementation, the simplified SAP adaptive sub-filters are transformed by the pipeline technique.

• The Transactions of the Korea Information Processing Society
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• v.7 no.12
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• pp.3986-3994
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• 2000

A multiple vector reductive processing occurs during the vector inner product operation ([C] = [A] $\bigodot$,$\square$ [B]) and proceeds at the hardware dyadic pipeline unit. Every scalar result has to be generated with the component merging delay time in the multiple vector reduction($\bigodot$). In this paper we propose a new design method by which the component merging time could be eliminated from the multiple reduction and the scalar results from the reduction($\bigodot$) could be generated nearly in the almost same condensed time as the input components are fel>ded in the dyadic pipeline unitlo) or the output components are drained out of the dyadic pipeline unit($\square$), so called a dedicated chained pipeline unit for only a inner product operation.