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http://dx.doi.org/10.13089/JKIISC.2005.15.5.3

Structure Analysis of ARS Cryptoprocessor based on Network Environment  

Yun, Yeon-Sang (Dept. of Information and Communication Engineering, Chungbuk Nat'1 University)
Jo, Kwang-Doo (Dept. of Information and Communication Engineering, Chungbuk Nat'1 University)
Han, Seon-Kyoung (Dept. of Information and Communication Engineering, Chungbuk Nat'1 University)
You, Young-Gap (Dept. of Information and Communication Engineering, Chungbuk Nat'1 University)
Kim, Yong-Dae (The Korea Intelligent Property Office)
Publication Information
Journal of the Korea Institute of Information Security & Cryptology / v.15, no.5, 2005 , pp. 3-11 More about this Journal
Abstract
This paper presents a performance analysis model based on an M/M/1 queue and Poisson distribution of input data traffic. The simulation on a pipelined AES system with processing rate of 10 rounds per clock shows $4.0\%$ higher performance than a non-pipelined version consuming 10 clocks per transaction. Physical implementation of pipelined AES with FPGA takes 3.5 times bigger gate counts than the non-pipelined version whereas the pipelined version yields only $3.5\%$ performance enhancement. The proposed analysis model can be used to optimize cost-performance of AES hardware designs.
Keywords
AES; Cryptoprocessor; Performance Analysis;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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