The Transactions of the Korea Information Processing Society (한국정보처리학회논문지)

Korea Information Processing Society (한국정보처리학회)
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On Design for Elimination of the Merging Delay Time in the Multiple Vector Reduction (Inner Product)

다중벡터감출처리(내적처리)에서 합병지연시간의 제거를 위한 설계

  • Published : 2000.12.01
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Abstract

A multiple vector reductive processing occurs during the vector inner product operation ([C] = [A] $\bigodot$,$\square$ [B]) and proceeds at the hardware dyadic pipeline unit. Every scalar result has to be generated with the component merging delay time in the multiple vector reduction($\bigodot$). In this paper we propose a new design method by which the component merging time could be eliminated from the multiple reduction and the scalar results from the reduction($\bigodot$) could be generated nearly in the almost same condensed time as the input components are fel>ded in the dyadic pipeline unitlo) or the output components are drained out of the dyadic pipeline unit($\square$), so called a dedicated chained pipeline unit for only a inner product operation.

다중 벡터감축처리는 벡터의 내적처리([C] =[A]$\bigodot$,$\square$ [B])에서 발생하며, 두 개의 입력포트를 갖는 파이프라인유니트에서 처리된다. 각각의 스칼라 결과값은 다중 벡터감축처리($\bigodot$)에서 요소들의 합병지연시간을 가져야 생성된다. 본 연구에서는 다중 감축처리에서 요소 합병지연시간이 제거되고, 감축처리($\bigodot$)로부터 스칼라 결과값들이 파이프라인($\square$) 입력시간과 거의 같게 생성될 수 있는 즉, 내적처리만을 위한 전용 체인 파이프라인 유니트 설계기법을 제안한다.

Keywords

References

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