• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9C
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• pp.771-777
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• 2010

This paper proposes a new signal detection method, called QR-OSIC with Candidates (QOC) method, for spatially multiplexed multiple input multiple output (MIMO) systems. By using the ordered successive interference cancellation (OSIC) algorithm and the maximum likelihood (ML) metric, the proposed method achieves near-ML performance without requiring a large number of candidates. Although the proposed method can be used for both hard and soft decoding systems, it is especially useful for soft decoding systems since the LLR values for all the bits can be efficiently computed without using LLR estimation. The proposed method is also suitable for VLSI implementation since it leads to fixed throughput system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.1090-1098
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• 1999

In this paper ERP-4 viterbi decoder for magnetic disk read channel is designed. The viterbi decoder consists of ACS circuit, path memory circuit, minimum detection circuit, and output selection circuit. In the viterbi decoder the number of state is reduced from 8 to 6 using (1,7) RLL codes and modulo comparison based on 2's complement arithmetic is applied to handle overflow problem of ACS module. Also to determine the correct symbol values in nonconvergent condition of path memory, pipelined minimum detector which determines path with minimum state metric is used. The EPR-4 viterbi decoder is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology and consists of about 15,300 transistors and has 250 Mbps data rates under 3.3 volts.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.1-10
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• 2008

In this paper, we designed a facial feature(eyes, a moult and a nose) detection hardware based on the ICT transform which was developed for face detection earlier. Our design used a pipeline architecture for high throughput and it also tried to reduce memory size and memory access rate. The algerian and its hardware implementation were tested on the BioID database, which is a worldwide face detection test bed, and its facial feature detection rate was 100% both in software and hardware, assuming the face boundary was correctly detected. After synthesizing the hardware on Dongbu $0.18{\mu}m$ CMOS library, its die size was $376,821{\mu}m^2$ with the maximum operating clock 78MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.124-129
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• 2013

This paper proposes a high-performance vector inner product calculation circuit for real-time object recognition based on SVM algorithm. SVM algorithm shows a higher detection rate than other object recognition algorithms. However, it requires a huge amount of computational efforts. Since vector inner product calculation is one of the major operations of SVM algorithm, it is important to implement a high-performance vector inner product calculation circuit for real-time object recognition capability. The proposed circuit adopts the pipeline architecture with six stages to increase the operating speed and makes it possible to recognize objects in real time based on SVM. The proposed circuit was described in Verilog HDL at RTL. For silicon verification, an MPW chip was fabricated using TSMC 180nm standard cell library. The operation of the implemented MPW chip was verified on the test board with test application software developed for the chip verification.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3C
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• pp.296-306
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• 2003

In this paper, algorithm for non-iterative decoding method is proposed and fractal image decoder based on non-iterative fractal decoding algorithm used general purpose digital signal processors is designed and implemented. The algorithm is showed that the attractor image can be obtained analytically whe n the image is encoded using the fractal algorithm proposed by Monro and Dudbridge, in which the corresponding domain block for a range block is fifed. Using the analytical formulas, we can obtain the attractor image without iteration procedure. And we get general formulas of obtained analytical formulas. Computer simulation results for various test images show that we can increase the image decoding speed by more than five times when we use the analytical formulas compared to the previous iteration methods. The fractal image decoder contains two ADSP2181's and perform image decoding by three stage pipeline structure. The performance tests of the implemented decoder is elapsed 31.2ms/frame decoding speed for QCIF data when all the frames are decoded. The results enable us to process the real-time fractal decoding over 30 frames/sec.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.49-54
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• 2007

As digital contents based on 3D graphics are increased, the requirement for low power 3D graphic hardware for mobile devices is increased. We design a transformation engine for mobile 3D graphic processor. We propose a simplified transformation engine for mobile 3D graphic processor. The area of the transformation engine is reduced by merging a mapping transformation unit into a projective transformation unit and by replacing a clipping unit with a selection unit. It consists of a viewing transformation unit a projective transformation unit a divide by w nit, and a selection unit. It can process 32 bit floating point format of the IEEE-754 standard or a reduced 24 bit floating point format. It has a pipelined architecture so that a vertex is processed every 4 cycles except for the initial latency. The RTL code is verified using an FPGA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.55-64
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• 2004

In this paper, we propose an efficient FFT algorithm for high speed multimedia communication systems, and present its pipeline implementation results. Since the proposed algorithm is based on the radix-4 butterfly unit, the processing rate can be twice as fast as that based on the radix-2$^3$ algorithm. Also, its implementation is more area-efficient than the implementation from conventional radix-4 algorithm due to reduced number of nontrivial multipliers like using the radix-23 algorithm. In order to compare the proposed algorithm with the conventional radix-4 algorithm, the 64-point MDC pipelined FFT processor based on the proposed algorithm was implemented. After the logic synthesis using 0.6${\mu}{\textrm}{m}$ technology, the logic gate count for the processor with the proposed algorithm is only about 70% of that for the processor with the conventional radix-4 algorithm. Since the proposed algorithm can be achieve higher processing rate and better efficiency than the conventional algorithm, it is very suitable for the high speed multimedia communication systems such as WLAN, DAB, DVB, and ADSL/VDSL systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.643-650
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• 2014

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator adopts redundant binary number systems and a pipelined architecture to improve throughput and speed. It performs arctangent operation using vectoring mode of DCORDIC(Differential COordinate Rotation DIgital Computer) algorithm. Fixed-point MATLAB simulations are carried out to determine the optimal bit-widths and number of iteration. The phase calculator has ben verified by FPGA-in-the-loop verification using MATLAB/Simulink. A test chip has been fabricated using a TSMC $0.18-{\mu}m$ CMOS process, and test results show that the chip functions correctly. It has 82,000 gates and the estimated throughput is 400 MS/s at 400Mhz@1.8V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.12
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• pp.2140-2145
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• 2008

We design and synthesize a 128-point FFT processor for multi-band OFDM, which can be applied to a UWB transceiver. The structure of a 128-point FFT processor is based on a Radix-2 FFT algorithm and a R2SDF pipeline architecture. The algorithm is efficiently modeled in VHDL and the result is simulated using Modelsim. Finally, they are synthesized on Xilinx Vertex-II FPGA, and an operational frequency of 18.7MHz has been obtained. It is expected that the proposed 128-point FFT processor can be applied to an entire FFT block as one of parallel processed FFTs. In order to obtain the enhanced maximum frequency of operation, we design the FFT module consisting of four 128-point FFT processors for parallel process. As a result, we achieve the performance requirement of computing the FFT module in multi-band OFDM symbol timing in 90nm ASIC process.