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http://dx.doi.org/10.5573/ieek.2013.50.11.124

MPW Chip Implementation and Verification of High-performance Vector Inner Product Calculation Circuit for SVM-based Object Recognition  

Shin, Jaeho (Department of Electronics Engineering, Hankuk University of Foreign Studies)
Kim, Soojin (Department of Electronics Engineering, Hankuk University of Foreign Studies)
Cho, Kyeongsoon (Department of Electronics Engineering, Hankuk University of Foreign Studies)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.11, 2013 , pp. 124-129 More about this Journal
Abstract
This paper proposes a high-performance vector inner product calculation circuit for real-time object recognition based on SVM algorithm. SVM algorithm shows a higher detection rate than other object recognition algorithms. However, it requires a huge amount of computational efforts. Since vector inner product calculation is one of the major operations of SVM algorithm, it is important to implement a high-performance vector inner product calculation circuit for real-time object recognition capability. The proposed circuit adopts the pipeline architecture with six stages to increase the operating speed and makes it possible to recognize objects in real time based on SVM. The proposed circuit was described in Verilog HDL at RTL. For silicon verification, an MPW chip was fabricated using TSMC 180nm standard cell library. The operation of the implemented MPW chip was verified on the test board with test application software developed for the chip verification.
Keywords
Vector inner product calculation; High-performance; SVM; Real-time object recognition; MPW;
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