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Hardware Implementation of Facial Feature Detection Algorithm  

Kim, Jung-Ho (Dept. of Electronics and Communications Engineering, Kwangwoon University)
Jeong, Yong-Jin (Dept. of Electronics and Communications Engineering, Kwangwoon University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea CI / v.45, no.1, 2008 , pp. 1-10 More about this Journal
Abstract
In this paper, we designed a facial feature(eyes, a moult and a nose) detection hardware based on the ICT transform which was developed for face detection earlier. Our design used a pipeline architecture for high throughput and it also tried to reduce memory size and memory access rate. The algerian and its hardware implementation were tested on the BioID database, which is a worldwide face detection test bed, and its facial feature detection rate was 100% both in software and hardware, assuming the face boundary was correctly detected. After synthesizing the hardware on Dongbu $0.18{\mu}m$ CMOS library, its die size was $376,821{\mu}m^2$ with the maximum operating clock 78MHz.
Keywords
Face detection; Facial feature detection; Embedded system;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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