• Title/Summary/Keyword: 파워 소모

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Visualization of Malwares for Classification Through Deep Learning (딥러닝 기술을 활용한 멀웨어 분류를 위한 이미지화 기법)

  • Kim, Hyeonggyeom;Han, Seokmin;Lee, Suchul;Lee, Jun-Rak
    • Journal of Internet Computing and Services
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    • v.19 no.5
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    • pp.67-75
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    • 2018
  • According to Symantec's Internet Security Threat Report(2018), Internet security threats such as Cryptojackings, Ransomwares, and Mobile malwares are rapidly increasing and diversifying. It means that detection of malwares requires not only the detection accuracy but also versatility. In the past, malware detection technology focused on qualitative performance due to the problems such as encryption and obfuscation. However, nowadays, considering the diversity of malware, versatility is required in detecting various malwares. Additionally the optimization is required in terms of computing power for detecting malware. In this paper, we present Stream Order(SO)-CNN and Incremental Coordinate(IC)-CNN, which are malware detection schemes using CNN(Convolutional Neural Network) that effectively detect intelligent and diversified malwares. The proposed methods visualize each malware binary file onto a fixed sized image. The visualized malware binaries are learned through GoogLeNet to form a deep learning model. Our model detects and classifies malwares. The proposed method reveals better performance than the conventional method.

Design of digital decimation filter for sigma-delta A/D converters (시그마-델타 A/D 컨버터용 디지털 데시메이션 필터 설계)

  • Byun, San-Ho;Ryu, Seong-Young;Choi, Young-Kil;Roh, Hyung-Dong;Nam, Hyun-Seok;Roh, Jeong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.2
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    • pp.34-45
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    • 2007
  • Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

Design of the Noise Margin Improved High Voltage Gate Driver IC for 300W Resonant Half-Bridge Converter (잡음 내성이 향상된 300W 공진형 하프-브리지 컨버터용 고전압 구동 IC 설계)

  • Song, Ki-Nam;Park, Hyun-Il;Lee, Yong-An;Kim, Hyoung-Woo;Kim, Ki-Hyun;Seo, Kil-Soo;Han, Seok-Bung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.10
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    • pp.7-14
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    • 2008
  • In this paper, we designed the HVIC(High Voltage Gate Driver IC) which has improved noise immunity characteristics and high driving capability. Operating frequency and input voltage range of the designed HVIC is up to 500kHz and 650V, respectively. Noise protection and schmitt trigger circuit is included in the high-side level shifter of designed IC which has very high dv/dt noise immunity characteristic(up to 50V/ns). And also, rower dissipation of high-side level shifter with designed short-pulse generation circuit decreased more that 40% compare with conventional circuit. In addition, designed HVIC includes protection and UVLO circuit to prevent cross-conduction of power switch and sense power supply voltage of driving section, respectively. Protection and UVLO circuit can improve the stability of the designed HVIC. Spectre and Pspice circuit simulator were used to verify the operating characteristics of the designed HVIC.

NIR reflecting properties of TiO2/Ag/TiO2 multilayers deposited by DC/RF magnetron sputtering (DC/RF 마그네트론 스퍼터링법을 이용한 TiO2/Ag/TiO2 하이브리드 다층박막의 적외선 반사 특성)

  • Kim, Seong-Han;Kim, Seo-Han;Song, Pung-Geun
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2016.11a
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    • pp.158-158
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    • 2016
  • 최근 화석연료의 고갈과 환경 보전 및 에너지 절약에 대한 관심이 높아짐에 따라 화석연료의 소비를 최소화하고 실내조건을 쾌적하게 유지하려는 연구가 진행되고 있다. 국내의 경우 전체 에너지 소비의 30%이상을 차지하고 있는 건물부문에서의 에너지 소비를 줄이기 위한 활발한 연구가 진행되고 있으며 이에 따른 에너지절약 소재개발이 활발하게 진행되고 있다. 1975년 이후 여러 차례에 걸친 단열강화 조치를 통해 건물에서의 에너지 소모를 줄이고 있었으나 건물의 외벽에 대한 사항으로 한정되어있었고, 또한 건물의 창 면적이 증가함에 따라 창을 통한 열손실량과 열획득량이 더욱 증가하게 되었다. 이러한 문제를 해결하기 위해 열반사유리에 대한 많은 연구가 진행되고 있다. 열반사유리는 근적외선(열선)영역의 빛을 반사시켜 실내의 열손실량 및 외부에서의 열획득량을 감소시켜 에너지의 소비를 줄일 수 있는 유리을 말한다. 이러한 열반사유리은 fresnel 방정식을 통해 빛의 파장대에 따른 반사율 및 투과도를 예측할 수 있는데, 다층박막구조인 Oxide-Metal-Oxide(OMO)구조는 Oxide의 높은 굴절률과 Metal의 낮은 굴절률을 통해 가시광영역대의 높은 투과도와 근적외선 영역의 높은 반사율을 얻을 수 있다. 또한 Metal층을 삽입함으로서 flexible한 코팅이 가능하고, 높은 carrier density와 mobility로 표면 플라즈몬 공명을 통해 특정 파장대의 반사율을 높일 수 있으므로 많은 연구가 진행되고 있다. $TiO_2$는 고굴절률 및 낮은 광흡수성의 특성을 가지는 산화물반도체로 기존의 $In_2O_3$계 산화물에 비해 값이 싸고 높은 안정성과 광촉매특성을 보이므로 외부에 노출된 환경에 적합한 재료이다. Ag는 저굴절률과 낮은 광흡수성을 가지는 재료로 금속층에 적합하다. 본 연구에서는 fresnel 방정식을 통해 반사도 및 투과도를 예측하고 마그네트론 스퍼터링법으로 다층박막을 열선인 적외선 영역에서의 반사율 및 반사 효율을 평가하였다. Index-matching 시뮬레이션을 통해 $TiO_2/Ag/TiO_2$ 다층박막의 투과도와 반사도를 이론적으로 검토하였다. 시뮬레이션 프로그램은 Macleod프로그램을 이용하였고 재료 각각의 굴절률은 Ellipsometry를 이용하여 측정하였다. 두께 40 nm 와 8 ~ 16 nm를 가지는 $TiO_2$층과 Ag층을 각각 RF/DC 마그네트론 스퍼터링법을 이용하여 Glass기판 위에 증착하였다. 직경 3 in 의 $TiO_2$, Ag 소결체 타깃을 이용하였고 스퍼터링 파워는 각각 200 W, 50 W로 설정하였고, 스퍼터링 가스는 Ar가스의 유량을 20 sccm으로 설정하였다. 작업압력은 모두 1 Pa로 설정하였고 타깃 표면의 불순물 및 이물질 제거를 위해 Pre-sputtering을 10분 진행하였다. 박막의 두께는 reflectometer와 Alphastep을 이용하여 측정하였고 Hall effect measurement를 이용하여 비저항, carrier density, mobility등 전기적 특성을 측정하였다. 또한 UV-VIS spectrometer와 USPM-RU-W NIR Micro-Spectrophotometer를 통해 광학적 특성을 측정하였고 계산 값과 비교분석하였다. 또한 열반사 특성을 평가하기 위해 직접 set-up한 장비를 이용하였다. 단열 박스에 샘플을 장착해 적외선 램프를 조사하였을 때의 열 반사효율을 평가하였고, IR Camera를 이용하여 단열 박스 내부의 온도 변화를 관찰하였다.

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A Novel High-speed CMOS Level-Up/Down Shifter Design for Dynamic-Voltage/Frequency-Scaling Algorithm (Dynamic-Voltage/Frequency-Scaling 알고리즘에서의 다중 인가 전압 조절 시스템 용 High-speed CMOS Level-Up/Down Shifter)

  • Lim Ji-Hoon;Ha Jong-Chan;Wee Jae-Kyung;Moon Gyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.6 s.348
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    • pp.9-17
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    • 2006
  • We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

A Microwave Push-Push VCO with Enhanced Power Efficiency in GaInP/GaAs HBT Technology (향상된 전력효율을 갖는 GaInP/GaAs HBT 마이크로파 푸쉬-푸쉬 전압조정발진기)

  • Kim, Jong-Sik;Moon, Yeon-Guk;Won, Kwang-Ho;Shin, Hyun-Chol
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.9
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    • pp.71-80
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    • 2007
  • This paper presents a new push-push VCO technique that extracts a second harmonic output signal from a capacitive commonnode in a negativegm oscillator topology. The generation of the $2^{nd}$ harmonics is accounted for by the nonlinear current-voltage characteristic of the emitter-base junction diode causing; 1) significant voltage clipping and 2) different rising and falling time during the switching operation of core transistors. Comparative investigations show the technique is more power efficient in the high-frequency region that a conventional push-push technique using an emitter common node. Prototype 12GHz and 17GHz MMIC VCO were realized in GaInP/GaAs HBT technology. They have shown nominal output power of -4.3dBm and -5dBm, phase noise of -108 dBc/Hz and -110.4 dBc/Hz at 1MHz offset, respectively. The phase noise results are also equivalent to a VCO figure-of-merit of -175.8 dBc/Hz and -184.3 dBc/Hz, while dissipate 25.68mW(10.7mA/2.4V) and 13.14mW(4.38mA/3.0V), respectively.

Analysis of Utilization and Maintenance of Major Agricultural machinery (Tractor, Combine Harvester and Rice Transplanter) (핵심 농기계(트랙터, 콤바인 및 이앙기) 이용 및 수리실태 분석)

  • Hong, Sungha;Choi, Kyu-hong
    • Journal of the Korean Society of International Agriculture
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    • v.30 no.4
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    • pp.292-299
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    • 2018
  • In a survey in which farmers were asked about their levels of satisfaction with agricultural machines, Japanese products scored higher than local products by 1.2, 1.3, and 1.4 times for tractors, combine harvesters, and rice transplanter, respectively. Japanese products corresponded to generally high satisfaction levels in terms of operating performance, operability, frequency of breakdowns, and durability, excluding sales price and after-sales services. Effective countermeasures through quality improvement are therefore necessary for Korean products. Furthermore, a survey of dealers showed that the components and consumables for core agricultural machines had high frequencies of breakdowns and repairs. Four major components of tractors represented 85.3% of all breakdowns and repairs, five components of combine harvesters represented 89.6%, and three components of rice transplanters represented 80.5%. Moreover, a comparison of the technological levels between local and imported machines showed that the local machines' levels were at 60-100% for tractors, 70-100% for combine harvesters, and 70-95% for rice transplanters. Small and mid-sized tractors, 4 interrow combine harvesters, and 6 interrow rice transplanters showed similar levels of technology. The results of the analysis suggest that action is urgently needed at a policy level to establish an agricultural machinery component research center for the development, production, and supply of commonly-used components, with the participation of manufacturers of agricultural machines and components, in order to enhance the competitiveness of local manufacturers and to revitalize the agricultural machine market.