• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.333-341
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• 2015

In this paper, a 0.5~4 GHz frequency synthesizer having good phase noise performance is proposed. Wideband output frequencies of the synthesizer were synthesized using DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology in order to obtain fast settling time. Also in order to get good phase noise performance, 2.4 GHz DDS clock was generated by VCO(Voltage Controlled Oscillator) which was locked by the 100 MHz reference oscillator using SPD(Sample Phase Detector). The phase noise performance of wideband frequency synthesizer was estimated and the results were compared with the measured ones. The measured phase noise of the frequency synthesizer was less then -121 dBc @ 100 kHz at 4 GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.10
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• pp.914-924
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• 1991

It has been generally used for PLL(Phase Locked Loop) to be synthesized randomly chosen frequency state, but the PLL locking time was inevitable element. A direct digital synthesizer. Which makes output frequency directly in sine wave by a phase accumulating method, could be leiminate the defect, although a phase distortion in frequency spectrum. In order to improve this disadvantage, the phase accumulating method is reconsidered in the side of he output wave formula expression. A new mechanism is proposed, and it is constructed by a most suitable logic elements. The spectrum of synthesized sine waveform is simulated and compared with a measured value, and it’s the coherence frequency hoppong state with the PN(Pseudo Noise) code sequence is confirmed. In this results, the power levels of phase distortion harmonics are decreased to 10~25dB and bandwidths are increased to 420kHz.

• Journal of Broadcast Engineering
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• v.13 no.4
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• pp.452-462
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• 2008

In this paper, we address issues associated with the real-time implementation of the MPEG-1/2 Layer-II (or MUSICAM) and MPEG-4 ER-BSAC decoders for Digital Multimedia Broadcasting (DMB) on TMS320C64x+ that is a fixed-point DSP processor with a clock speed of 330 MHz. To achieve the real-time requirement, they should be optimized in different steps as follows. First of all, a C-code level optimization is performed by sharing the memory, adjusting data types, and unrolling loops. Next, an algorithm level optimization is carried out such as the reconfiguration of bitstream reading, the modification of synthesis filtering, and the rearrangement of the window coefficients for synthesis filtering. In addition, the C-code of a synthesis filtering module of the MPEG-1/2 Layer-II decoder is rewritten by using the linear assembly programming technique. This is because the synthesis filtering module requires the most processing time among all processing modules of the decoder. In order to show how the real-time implementation works, we obtain the percentage of the processing time for decoding and calculate a RMS value between the decoded audio signals by the reference MPEG decoder and its DSP version implemented in this paper. As a result, it is shown that the percentages of the processing time for the MPEG-1/2 Layer-II and MPEG-4 ER-BSAC decoders occupy less than 3% and 11% of the DSP clock cycles, respectively, and the RMS values of the MPEG-1/2 Layer-II and MPEG-4 ER-BSAC decoders implemented in this paper all satisfy the criterion of -77.01 dB which is defined by the MPEG standards.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.6 no.2
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• pp.126-137
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• 2007

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed. And we design the phase-to-sine converter using the phase accumulator of parallel type for generating the high frequency. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is saved by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.12
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• pp.1243-1250
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• 2014

In this paper, a wideband DDS module covering the frequency range from 0.5 to 1.1 GHz was designed and fabricated. The clock frequency of the DDS was selected 2.4 GHz in order for 600 MHz output bandwidth. Multiple spurious cancelling signals having same amplitude and $180^{\circ}$ phase difference compared to the spurious were created at the additional path and added to the output signal within DDS for the spurious performance improvement. The fabricated DDS module showed better spurious performance than the commercial DDS one more than 10 dB and frequency tuning time was 340 ns below.

• Journal of KIISE:Software and Applications
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• v.37 no.8
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• pp.647-652
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• 2010

Esterel is an imperative synchronous language well-adapted to control-intensive systems. When an Esterel program is translated to a circuit, the synchronizer of a parallel statement may be executed more than once in a clock; the synchronizer is called schizophrenic. Existing compilers cure the problems of schizophrenic parallel synchronizers using logic duplications. This paper proposes the conditions under which a synchronizer causes no problem in circuits when it is executed more than once in a clock. In addition we design a detection algorithm based on those conditions. Our algorithm detects schizophrenic parallel synchronizers that have to be duplicated in Esterel source codes so that compilers can save the size of synthesized circuits

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.6
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• pp.55-61
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• 2013

In this paper, we describe design and implementation of audio encoder/decoder for voice synthesis. It uses the encoding of difference value of successive samples instead of the original sample value. and has the compression ratio of 4. The function is verified by using FPGA and the performance is measured by the fabricated chip using $0.35{\mu}m$ standard CMOS process. The system clock is 16.384MHz. The measured THD+n is from -40dB to -80dB with frequency variation and the power consumption is about 80mW. It is suited for the mobile application of high audio quality and low power consumption.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.36-43
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• 1999

A new design of a Direct Digital Frequency Synthesizer(DDFS) is presented, where a pipelined Coordinate Rotate Digital Computer(CORDIC) circuit is employed to calculate amplitude values of all the phase angles of sinusoidal waveforms produced. a near-optimal number of pipeline stages is determined based on an error analysis of calculated amplitude values in terms of the number of bits. The DDFS was implemented using a field programmable gate array, yielding a stable operating frequency of 11.75MHz. The measurement results show higher resolution, faster operating speed and simpler fabrication process, compared to ROM-based counterparts. The CORDIC-based DDFS yields 5 times higher resolution than conventional ROM-based versions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.361-368
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• 2003

A new high-speed direct digital frequency synthesizer using a low power pipelined parallel accumulator is proposed. The proposed pipelined parallel accumulator uses both pipelining and paralleling techniques to increase speed and to reduce power consumption. The 2-pipelined 2-parallel accumulator only consumes 66% and 69% power of the 4-pipelined accumulator and the 4-parallel accumulator respectively with the same throughput. The proposed accumulator can achieve higher throughput with smaller area and less power consumption in lower clock frequency. All circuit simulations and implementations are based on a 0.35um CMOS process with VCC = 3.3V.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.6
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• pp.48-55
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• 2001

This paper presents a 1.8 GHz CMOS frequency synthesizer with high-speed on-chip pseudo 2-stage ring VCO. We introduce and analysis the conditions in which the ring VCO can oscillate. For high speed operation, we propose the pseudo 2-stage ring VCO that eliminates dummy loads. It can operate up to 1.87 GHz with 0.6 m CMOS process, which shows 21.3% improvement aginst the conventional 4-stage ring VCO in the aspect of the speed. When the frequency synthsizer with the psedo 2-stage ring VCO is locked at 1.85GHz, the jitter measured to 24 psec. The proposed VCO and the frequency synthesizer are directly applicable to high speed clocky synhtesizers.