Reducing False Alarms in Schizophrenic Parallel Synchronizer Detection for Esterel |
Yun, Jeong-Han
(KAIST 전산학과)
Kim, Chul-Joo (삼성전자 Digital Media & Communications R&D Center) Kim, Seong-Gun (KAIST 전산학과) Han, Tai-Sook (KAIST 전산학과) |
1 | A. Benveniste, P. Caspi, S. A. Edwards, N. Halbwachs, P. Le Guernic, and R. de Simone, "The synchronous languages 12 years later," Proceedings of the IEEE Embedded Systems, vol.91(1), pp.64-83, 2003. |
2 | G. Berry. The Constructive Semantics of Pure Esterel. Draft book available at http://www.inria.fr/meije/esterel/esterel-eng.html, 1999. |
3 | D. Potop-Butucaru, S. A. Edwards, and G. Berry. Compiling Esterel. Springer, 2007. |
4 | Esterel Technologies. The Esterel v7 Reference Manual Version v7.30. initial IEEE standardization proposal. Esterel Technologies, 679 av. Dr. J. Lefebvre 06270 VilleneuveLoubet, France, November, 2005. |
5 | O. Tardieu and R. de Simone, "Loops in Esterel," Transactions on Embedded Computing Systems, vol.4, no.4, pp.708-750, 2005. DOI |
6 | K. Schneider, J. Brandt, and T. Schuele, "A verified compiler for synchronous programs with local declarations," Electronic Notes in Theoretical Computer Science, vol.153, no.4, pp.71-97, 2006. DOI ScienceOn |
7 | G. Berry, "Circuit design and verification with Esterel v7 and Esterel Studio," IEEE International High-Level Design, Validation, and Test Workshop, pp.133-136, 2007. |
8 | M. Yoeli and S. Rinon, "Application of ternary algebra to the study of static hazards," Journal of ACM, vol.11, no.1, pp.84-97, 1964. DOI |
9 | S. Malik, "Analysis of cyclic combinational circuitsM" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.13, no.7(7), pp.950-956, 1994. DOI ScienceOn |
10 | M. D. Riedel and J. Bruck, "Cyclic boolean circuits," Journal of Discrete Applied Mathematics, 2009. |
11 | C. Kim, J. Yun, S. Seo, K. Choe, and T. Han, "Over-approximated Control Flow Graph Construction on Pure Esterel," IEICE Transactions on Information and Systems, vol.E93-D, no.5, May 2010 (accepted). |
12 | J. Yun, C. Kim, S. Seo, T. Han, and K. Choe, "Refining schizophrenia via graph reachability in Esterel," 7th ACM-IEEE International Conference on Formal Methods and Models for Codesign, 2009. |
13 | S. Ramesh, Ramesh's homepage. http://www.cse.iitb.ac.in/-ramesh |
14 | N. Halbwachs, Synchronous Programming of Reactive Systems, Kluwer Academic Publishers, 1993. |