Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A design and analysis of Pseudo 2-stage ring CMOS VCO for 1.8-GHz Frequency Synthesizer

1.8-GHz 주파수 합성기용 가상 2단 링 CMOS VCO의 설계 및 분석

  • Lee, Soon-Seob (ASIC Design Lab., Electronic Engineering, Korea University) ;
  • Kim, Se-Yeob (Integrant Technologies Inc.) ;
  • Nam, Kee-Hyun (ASIC Design Lab., Electronic Engineering, Korea University) ;
  • Cho, Kyoung-Sun (ASIC Design Lab., Electronic Engineering, Korea University) ;
  • Gal, Chang-Lyung (ASIC Design Lab., Electronic Engineering, Korea University) ;
  • Kim, Soo-Won (ASIC Design Lab., Electronic Engineering, Korea University)
  • 이순섭 (고려대학교 전자공학과, ASIC 설계 연구실) ;
  • 김세엽 (주 인티그런트 테크놀로지즈) ;
  • 남기현 (고려대학교 전자공학과, ASIC 설계 연구실) ;
  • 조경선 (고려대학교 전자공학과, ASIC 설계 연구실) ;
  • 갈창룡 (고려대학교 전자공학과, ASIC 설계 연구실) ;
  • 김수원 (고려대학교 전자공학과, ASIC 설계 연구실)
  • Published : 2001.12.31
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Abstract

This paper presents a 1.8 GHz CMOS frequency synthesizer with high-speed on-chip pseudo 2-stage ring VCO. We introduce and analysis the conditions in which the ring VCO can oscillate. For high speed operation, we propose the pseudo 2-stage ring VCO that eliminates dummy loads. It can operate up to 1.87 GHz with 0.6 m CMOS process, which shows 21.3% improvement aginst the conventional 4-stage ring VCO in the aspect of the speed. When the frequency synthsizer with the psedo 2-stage ring VCO is locked at 1.85GHz, the jitter measured to 24 psec. The proposed VCO and the frequency synthesizer are directly applicable to high speed clocky synhtesizers.

본 논문에서 고속 가상 2단 링VCO를 내장한 1.8 GHz 주파수 합성기를 0.6m CMOS 기술을 이용하여 구현하였다. 고속 동작을 위한 링 발진기의 발진 조건을 제시하고, 출력 부하를 줄인 가상 2단 링 형태의 발진기를 제안하여 최고 1.87 GHz의 발진을 확인하였다. 이는 기존의 4단 링 VOC에 비해 21.3%의 속도가 향상된 것이다. 제안된 VCO와 함께 집적된 주파수 합성기는 위상 고정시 24ps 지터가 측정되어 고속 주파수 합성기나 고속 클럭 발진기 등에 응용이 가능함을 입증하였다.

Keywords

References

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