1 |
A Direct Digital Frequency Synthesizer Using A New ROM Compression Method
/
[
Byung Do Yang;Lee Sup Kim
] /
ESSCIRC2001
|
2 |
J. Vankka, 'Methods of Mapping from Phase to Sine Amplitude in Direct Digital Synthesis', IEEE Tr. on ultrasonics, ferroelectrics, and frequency control, Mar. 1997, pp. 526-534
DOI
ScienceOn
|
3 |
Byung-Do Yang and Lee-Sup Kim, 'A Direct Digital Frequency Synthesizer Using A New ROM Compression Method', ESSCIRC2001, pp. 288-291
|
4 |
H. T. Nicholas, and H. Samueli, 'A 150-MHz direct digital frequency synthesizer in 1.25um CMOS with -90-dBc spurious performance', IEEE JSSC, Dec. 1991, pp. 1959-1969
|
5 |
L. K. Tan, and H. Samueli, 'A 200-MHZ quadrature digital synthesizer', IEEE JSSC, Mar. 1995, pp. 193-200
|
6 |
J. Chow, F. F. Lee, P. M. Lau, C. G. Ekroot, and J. E. Hornung, '1.25GHz 26-bit pipelined digital accumulator', GaAs IC Symp. Tech. Dig., Nov. 1988, pp. 131-134
DOI
|
7 |
Matthew Thompson, 'Low-Latency, High-Speed Numerically Controlled Oscillator Using Progression-of-States Technique', IEEE JSSC, Jan. 1992, pp. 113-117
DOI
ScienceOn
|