• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.451-452
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• 2009

IEEE 1588은 대칭 망에서만 정확한 클럭 동기화를 제공하는 문제점이 있다. 이를 해결하기 위해 Enhanced IEEE 1588이 제안되었지만, 단순히 비대칭 링크 율만을 고려했다는 한계를 가진다. 본 논문에서는 비대칭 율이 매우 크며 클럭 동기화 정확성에 영향을 미칠 수 있는 요소를 사용한 비대칭 망 환경에서도 정확한 클럭 동기화를 제공할 수 있는 새로운 알고리즘을 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.929-935
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• 2003

An analog/digital mixed mode ASIC for network synchronization of ATM switching system has been designed and fabricated. This ASIC generates a 234.7/46.94 ㎒ system clock and 77.76/19.44 ㎒ user clock using 46.94 ㎒ transmitted clocks from other systems. It also includes digital circuits for checking and selecting of the transmitted clocks. For effective ASIC design, full custom technique is used in 2 analog PLL circuits design, and standard cell based technique is used in digital circuit design. Resistors and capacitors for analog circuits are specially designed which can be fabricated in general CMOS technology, so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology with no expensive. Testing results show stable 234.7 ㎒ and 19.44 ㎒ clocks generation with each 4㎰ and 17㎰ of low ms jitter.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.2
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• pp.95-99
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• 2005

This paper presents an accurate recovery method of the reference clock which is needed for network synchronization in two-way satellite multimedia systems compliant with DVB-RCS specification and which use closed loop method for burst synchronization. In these systems, the remote station transmits TDMA burst via return link. For burst synchronization, it obtains reference clock from program clock reference (PCR) defined by MPEG-2 system specification. The PCR is generated periodically at the hub system by sampling system clock which runs at 27MHz $\pm$ 30ppm. Since the reference clock is recovered by means of digital PLL(DPLL) using imprecise PCR values due to variable random jitter, the recovered clock frequency of remote station doesn't exactly match reference clock of hub station. We propose a robust recovery method of reference clock against random delay jitter The simulation results show that the recovery error is remarkably decreased from 5 clocks to 1 clock of 27MHz relative to the general DPLL recovery method.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.10
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• pp.1123-1130
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• 2015

Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

• The KIPS Transactions:PartC
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• v.18C no.1
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• pp.7-14
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• 2011

Power analysis attack on low-power consumed security devices such as smart cards is very powerful, but it is required that the correlation between the measured power signal and the mid-term estimated signal should be consistent in a time instant while running encryption algorithm. The power signals measured from the security device applying the random clock do not match the timing point of analysis, therefore random clock is used as counter measures against power analysis attacks. This paper propose a new constant pitch based time alignment for power analysis with random clock power trace. The proposed method neutralize the effects of random clock used to counter measure by aligning the irregular power signals with the time location and size using the constant pitch. Finally, we apply the proposed one to AES algorithm within randomly clocked environments to evaluate our method.

• The Transactions of the Korea Information Processing Society
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• v.5 no.3
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• pp.862-872
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• 1998

In this paper, we developed a delay test architecture and test procedure for clocked sequential circuit. In addition, we analyze the problems of conventional and previous method on delay test for clocked sequential circuit in IEEE 1149.1. This paper discusses several problems of Delay test on IEEE 1149.1 for clocked sequential circuit. Previous method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a method called ARCH-S, is based on a clock counting technique to generate continuous clocks for clocked input of CUT. A 4-bit counter is selected for the circuit under test. The simulation results ascertain the aecurate operation and effectiveness of the proposed architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7B
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• pp.989-995
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• 2001

흔히 전송매체와 연결되는 물리계층에서는 수신된 데이터열에서 동기를 획득하는 과정이 필요하다. 기가비트 이더넷에서는 PMA에서 PCS로 데이터열을 전송할 때 62.5MHz 두 개의 클럭에 맞추어 교대로 보내는 절차를 표준안으로 채택하고 있기 때문에 수신된 데이터열을 처리하기 위한 125MHz 클럭을 생성해내는 PLL이 필요하다. 그러나 PLL은 구현하기가 어렵다. 다른 대안들로는 FIFO를 활용하는 방법과 62.5MHz 클럭을 이용한 이중 데이터열 처리 방법 등이 있다. FIFO를 이용한 방법에서는 오버플로우가 발생할 수 있으며, 이중 데이터열 처리 방법에서는 표준안과 다른 별도의 수신부 설계가 필요하다. 본 논문에서는 언급한 방법들을 사용하지 않으면서도 표준안을 따르며 비용 효과적인 하나의 방안으로 송신부 클럭에 수신된 데이터열을 재정렬 시킬 수 있는 DSM(Divide-Select-Merge) 방법을 제안한다.

• Korean Journal of Optics and Photonics
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• v.11 no.6
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• pp.400-404
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• 2000

All-optical clock recovery from a 10 Gb/s RZ signal has been demonstrated using an actively mode-locked figure-eight laser incorporating a semiconductor optical amplifier in the loop-mirror scheme. Optical pulses with 10 ps pulse width were modulated by a LiNb03 external modulator at $2^{23}-1$ PRES and injected into the clock recovery circuit to extract optical pulses with 12 ps width. Regeneration of the original bit pattern has been accomplished by modulating the recovered clock with the same modulator, and no power penalty was observed at $10^{11}$..

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.259-262
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• 2000

본 논문은 전탐색 블럭매칭 움직임추정 VLSI 구조에서 클럭당 두연산(하나는 클럭의 상향에지, 하나는 하향에지에서 동작)을 수행하는 PE(Processing Element)를 교번적으로 결선, 클럭의 상향에지는 물론 하향에지에서도 동작하도록 하는 방식으로 클럭 사이클수를 줄이는 VLSI 구조를 제안한다 기존 구조에 그대로 적용되는 본 방법은 공급 데이타폭이 2 배, PE 의 HW 복잡도가 1.5 배 절대차 합 연산의 복잡도가 2 배로 늘어나 전체 하드웨어가 복잡해지나, PE수를 2배로 하여 클럭사이클수를 줄이는 방법에 비해서는 매우 효율적이다. 본 제안 구조는 계층적 움직임 추정 알고리듬을 사용한 MPEG-2 움직임 추정기 개발의 설계에 적용하여 기능과 HW 복잡도를 확인하였다.