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Implementation of 234.7 MHz Mixed Mode Frequency Multiplication & Distribution ASIC  

권광호 (한서대학교 전자공학과)
채상훈 (호서대학교 전자공학과)
정희범 (한국전자통신연구원 반도체원천연구소 집적회로연구부)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.28, no.11A, 2003 , pp. 929-935 More about this Journal
Abstract
An analog/digital mixed mode ASIC for network synchronization of ATM switching system has been designed and fabricated. This ASIC generates a 234.7/46.94 ㎒ system clock and 77.76/19.44 ㎒ user clock using 46.94 ㎒ transmitted clocks from other systems. It also includes digital circuits for checking and selecting of the transmitted clocks. For effective ASIC design, full custom technique is used in 2 analog PLL circuits design, and standard cell based technique is used in digital circuit design. Resistors and capacitors for analog circuits are specially designed which can be fabricated in general CMOS technology, so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology with no expensive. Testing results show stable 234.7 ㎒ and 19.44 ㎒ clocks generation with each 4㎰ and 17㎰ of low ms jitter.
Keywords
Frequency multiplication & distribution ASIC; Mixed mode design; Clock generation; Jitter;
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