• Proceedings of the Korean Ceranic Society Conference
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• 2000.10a
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• pp.182.2-182
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• 2000

• Proceedings of the Materials Research Society of Korea Conference
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• 2005.05a
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• pp.128-128
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• 2005

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.901-902
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• 2006

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 1998.11a
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• pp.29-30
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• 1998

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.163.2-163.2
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• 2010

In this work, nano-flake shaped nickel oxide (NiO) films were synthesized by chemical bath deposition technique for electrochemical capacitors. The deposition was carried out for 1 and 2 h at room temperature using nickel foam as the substrate and the current collector. The structure and morphology of prepared NiO film were characterized by X-ray diffraction (XRD) and scanning electron microscopy (SEM). And, electrochemical properties were characterized by cyclic voltammetry, galvanostatic charge-discharge, and AC impedence measurement. It was found that the NiO film was constructed by many interconnected NiO nano-flakes which arranged vertically to the substrate, forming a net-like structure with large pores. The open macropores may facilitate the electrolyte penetration and ion migration, resulted in the utilization of nickel oxide due to the increased surface area for electrochemical reactions. Furthermore, it was found that the deposition onto nickel foam as substrate and curent collector led to decrease of the ion transfer resistance so that its specific capacitance of a NiO film had high value than NiO nano flake powder.

• Journal of the Korean Electrochemical Society
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• v.13 no.4
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• pp.223-234
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• 2010

In this review, the theory and applications of the complex capacitance analysis, which can be utilized in analyzing capacitor-like electrochemical systems, were summarized. Theoretically, it was suggested that the imaginary capacitance plots (Cim vs. log f) can provide a simple way to analyze electrochemical characteristics of capacitive systems, without complicated mathematical calculations. The usefulness of the complex capacitance analysis has been demonstrated by applying it to analyze EDLC characteristics of practical porous carbon electrodes, ionic conductivities inside small pores, and ionic resistances in the catalyst layers of polymer electrolyte membrane fuel cells.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2010.04a
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• pp.276-277
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• 2010

This paper deals with energy storage system for saving the energy of RTGC(rubber tired gantry crane). Advantage and disadvantage of battery, super-capacitor, and flywheel as an energy storage system were surveyed. Even if a flywheel energy storage system includes some problems such as manufacturing technique and high price, it is surveyed with a promising energy storage system In addition, RTGCs using battery or flywheel as the energy storage system were quantitatively presented through a survey of literatures. It was found that the both RTGC with those systems can reduced the waste of energy.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.369-370
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• 2009

전력선 통신용 접촉식 커플러의 제조 방법 확립과 응용 가능성을 파악하기 위해 440V이하의 저압용 3상 4선식 접촉식 커플러를 설계 및 제조하였다. 60Hz의 교류 전압 신호를 차단하는 캐패시터의 용량이 증가할수록 삽입 손실의 증가하였으며, 68nF의 캐패시터를 적용하여 90~450kHz, 2~30MHz의 전력선통신 주파수 대역에서 최소 삽입 손실 특성을 얻었다. 커플링 트랜스의 권선수 증가는 전자계 결합계수의 상승으로 자기유도 효율이 증가하여 삽입 손실 특성이 증가하였으며. 6턴 이상의 권선수에서는 거의 일정한 삽입 손실 특성을 나타내었다. 설계 완료된 접촉식 커플러를 이용하여 전력선 통신 주파수인 90~450kHz, 2~30MHz 대역에서 $-2\pm1dB$의 삽입 손실 특성을 얻었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.6
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• pp.1128-1135
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• 2001

In this paper, a new HSG-Si formation technology, "seeding method', which employs Si$_2$H$_{6}$-molecule irradiation and annealing, was applied for realizing 64Mbit DRAMs. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous-doped amorphous-Si electrode. The new HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors. In this technique, optimum process conditions of the phosphorous concentration, storage polysilicon deposition temperature and thickness of hemispherical grain silicon are in the range of 3.0-4.0E19atoms/㎤, 53$0^{\circ}C$ and 400$\AA$, respectively. In the 64M bit DRAM capacitor using optimum process conditions, limit thickness of dielectric nitride is about 65$\AA$.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.747-752
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• 2014

This paper relates 10% shrink from $0.13{\mu}m$ design for logic devices as well as input and output (I/O) circuits, different from the previous shrink methodologies which shrink only core device. Thin gate oxide was changed to decoupled plasma nitridation(DPN) oxide as a thin gate oxide (1.2V) to reduce the flicker noise, resulting in three to five times lower flicker noise than pre-shrink process. Unavoidable issue by shrink is capacitor for this normally metal insulator metal (MIM). To solve this issue, 20% higher unit MIM capacitor ($1.2fF/{\mu}m^2$) was developed and its performance were evaluated.