• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.37-43
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• 2006

Surface roughness and hardness of the electroplated Sn were characterized with variations of electroplating current density and current mode. The Sn electroplated at $5{\sim}50mA/cm^{2}$ exhibited the surface roughness of $2.0{\sim}2.4{\mu}m$. The Sn electroplated with pulse current mode exhibited low surface roughness compared one processed with direct current mode. With surface annealing at $300^{\circ}C$ for 3 sec using halogen lamp, surface roughness of the Sn bump was substantially reduced to $1{\mu}m$. The Sn electroplated at $5{\sim}50mA/cm^{2}$ exhibited the hardness of 10 Hv. Low contact resistances of $33{\sim}17m{\Omega}$ were obtained for specimens flip-chip bonded with Sn bumps.

• Korean Journal of Optics and Photonics
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• v.24 no.6
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• pp.342-346
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• 2013

We present the thermal analysis result of die bonding for a high power LED package using a metal hybrid silicone adhesive structure. The simulation structure consists of an LED chip, silicone die adhesive, package substrate, silicone-phosphor encapsulation, Al PCB and a heat-sink. As a result, we demonstrate that the heat generated from the chip is easily dissipated through the metal structure. The thermal resistance of the metal hybrid structure was 1.662 K/W. And the thermal resistance of the total package was 5.91 K/W. This result is comparable to the thermal resistance of a eutectic bonded LED package.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.8
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• pp.3301-3306
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• 2012

In LED chip packaging, die bonding is a very important process which fixes the LED chip on the lead frame to provide enough strength for the next process. Conventional pick-up device of the die bonder is simply operated by up and down motion of a collet and an ejector pin. However, this method may cause undesired problems such as position misalignment and/or severe die damage when the pick-up device reaches the die. In this study, to minimize the position alignment error and die damage, a die bonder is developed by adopting a new pick-up head for precise alignment and high speed feeding. To evaluate structural stability of the designed system, required finite element model of the die bonder is generated, and structural analysis is performed. Vibration analysis of the pick-up head is also performed using developed finite element model at operation frequency range. As a result of the analysis, deformation, stress, and natural frequency of the die bonder are investigated.

• Journal of the Korean institute of surface engineering
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• v.28 no.2
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• pp.67-76
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• 1995

The microstructure of 95wt.%Pb/5wt.%Sn and 63wt.%Sn/37wt.%Pb solders for flip chip bonding process has been characterized. Solders were deposited by thermal evaporation and reflowed in the conventional furnace or by rapid thermal annealing(RTA) process. As-deposited films show columnar structure. The microstructure of furnace cooled 63Sn/37Pb solder shows typical lamellar form, but that of RTA treated solder has the structure showing an uniform dispersion of Pb-rich phase in Sn matrix. The grain size of 95Pb/5Sn solder reflowed in the furnace is about $5\mu\textrm{m}$, but the grain size of RTA treated solder is too small to be observed. The microstructure in 63Sn/37Pb solder bump shows the segregation of Pb phase in the Sn rich matrix regardless of reflowing method. The 63Sn/37Pb solder bump formed by RTA process shows more uniform microstructure. These result are related to the heat dissipation in the solder bump.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.29-33
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• 2002

본 논문은 자기 바이어스(self bias)를 이용한 PCS 대역용 하이브리드 전력 저잡음 증폭기(power LNA) 모듈에 관한 것으로 GaAs p-HEMT 칩을 세라믹 기판에 실장하여 와이어 본딩과 주변 매칭을 통해 고주파 손실을 줄이고 온도 변화에 대한 안정성과 1.2㏈의 저잡음, 21~23㏈m의 P$_1$㏈를 실현하였다. 10mm$\times$10mm 크기로 표면 실장이 되도록 단자를 cut-line 형태로 모듈화 하여 안정성과 신뢰성을 향상시켰고 또한 저가격화를 실현하였다.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.25-29
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• 2002

We have fabricated a vertical trench Hall device which is sensitive to the magnetic field parallel to the sensor surface. The vertical trench Hall device has been built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried $SiO_2$ layer and surround trench define active device volume. Sensitivity up to 150 V/AT has been measured.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.75-75
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• 2010

3D 패키징 기술은 전기소자의 소형화, 고용량화, 저전력화, 높은 신뢰성등의 요구와 함께 그 중요성이 대두대고 있다. 이러한 3D 패키징의 연결방법은 와이어 본딩 또는 플립칩등의 기존의 방법에서 TSV(Through Silicon Via)를 이용하여 적층하는 방법이 주목받고 있다. TSV는 기존의 와이어 본딩과 비교하여 고집적도, 빠른 신호전달, 낮은 전력소비 등의 장점을 가지고 있어 많은 연구가 진행되고 있다. TSV의 세부 공정 중 비아필링(Via filling)기술은 I/O수 증가와 미세피치화에 따른 비아(Via) 직경의 감소 및 종횡비(Via Aspect Ratio)증가로 인해 기존 필링 공정으로는 한계가 있다. 기존의 비아 홀(Via hole)에 금속을 필링하기 위한 방법으로 전기도금법이 많이 사용되고 있으나, 전기도금법은 전기도금액 조성, 첨가제의 종류, 전류밀도, 전류모드 등에 따라 결과물에 큰 차이가 발생되어, 최적공정조건의 도출이 어렵다. 또한 20um이하의 비아직경과 높은 종횡비로 인하여 충진시 void형성등의 문제점이 발생하기도 한다. 본 연구에서는 용융솔더와 진공을 이용하여 비아를 필링시켰다. 이 방법은 관통된 비아가 형성된 웨이퍼 양단에 압력차를 주어, 작은 직경을 갖는 비아 홀의 표면장력을 극복하고, 용융상태의 솔더가 관통된 비아 홀 내부로 필링되는 방법이다. 관통 비아홀이 형성 된 웨이퍼 위에 솔더페이스트를 $250^{\circ}C$이상 온도를 가해 용융상태로 만든 후 웨이퍼 하부에 진공을 형성하여 필링하는 방법과 용융솔더를 노즐을 통하여 위쪽으로 유동시켜 그 위에 비아홀이 형성된 웨이퍼를 접촉하고 웨이퍼 상부에 진공을 형성하여 필링하는 방법으로 실험을 각각 실시하였다. 이 때, 웨이퍼 두께는 100um이하이며 홀 직경은 20, 30um, 웨이퍼 상부와 하부의 진공차는 약 0.02~0.08Mpa, 진공 유지시간은 1~3s로 실시하여 최적 조건을 고찰하였다. 각 조건에 따른 필링 후 단면을 전자현미경(FE-SEM)을 통해 관찰하였다. 실험 결과 0.04Mpa 이상에서 1s내의 시간에 모든 비아홀이 기공(Void)없이 완벽하게 필링되는 것을 관찰하였으며 이 결과는 기존의 방법에 비하여 공정시간을 감소시켜 생산성이 대폭 향상 될 수 있는 방법임을 확인하였다.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.