• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.2
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• pp.8-13
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• 1999

In this paper, an analytical threshold voltage model is proposed by replacing the conventional GCA(Gradual Channel Approximation) with the assumption that a normal depletion layer width in the intrinsic region will vary quasi-linearly according to the channel direction. Derived threshold voltage expression is written as a function of the effective channel length, drain voltage, substrate bias voltage, substrate doping concentration, and the oxide thickness. Calculated results show almost similar trends with BSIM3v3's results in a satisfactory accuracy.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.693-695
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• 2012

This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET as the device to be able to use until nano scale has the adventage to reduce the short channel effects. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change od the breakdown voltage for gate oxide thickness and channel thickness.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.35 no.9
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• pp.891-896
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• 2011

In this study, experiments were carried out to investigate the convective heat transfer characteristics of rectangular microchannels. The sample used in the experiments contained 20 rectangular microchannels in parallel. The channels had a hydraulic diameter of 700 ${\mu}m$. Distilled water was used as the working fluid. In the experiments, the Reynolds number ranged from 400 to 800, heat flux ranged from 35 to 85 kW/$m^2$, and the inlet fluid temperature was $20^{\circ}C$. As a result, the convective heat transfer coefficient increased upon increasing the Reynolds number and ranged from 4.6 to 6.4 kW/$m^2/^{\circ}C$ in the thermally fully developed region. Moreover, the higher the Reynolds number, the longer the thermal entry length in the rectangular microchannels. However, it was observed that a variable heat flux did not affect the thermal entry length. In conclusion, a correlation was proposed to indicate the heat transfer characteristics in a thermally fully developed region.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.2
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• pp.1-6
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• 1983

The reduction of threshold voltage and punchthrough voltage of short channel MOS transistors has been measured experimentally with silicon gate NMOS transistors. The effects of the gate oxide thickness and substrate doping concentration on the threshold voltage and punch-through voltage have also been measured with sample devices with boron implantation and gate oxide thickness of 50 nm and 70 nm. Hot electron emission has been measured by floating gate method for the samples with 3 ${\mu}{\textrm}{m}$ channel length. It has been concluded from this measurement that hot electron emission is not significant for the channel length of 3${\mu}{\textrm}{m}$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.470-473
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• 2000

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased patting density. The devices are scaled down day by day. Therefore, This paper investigates how MOSFET structures influence on transport properties in according to change of channel length and bias and, observes impact ionization between the drain and the gate. This paper proposes three models, i.e., conventional MOSFET, LDD MOSFET and EPI MOSFET. The gate lengths are 0.3$\mu\textrm{m}$ 0.15$\mu\textrm{m}$, 0.075$\mu\textrm{m}$ and scaling factor is λ = 2. We have presented MOSFET's characteristics such as I-V characteristic, impart ionization, electric field, using the TCAD. We have analyzed the adaptive channel and doping influences

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.15-22
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• 2008

The bulk-planer MOSFET has a scaling limitation due to the short channel effect (SCE). The Double-Gate MOSFET (DG-MOSFET) is a next generation device for nanoscale with excellent control of SCE. The quantum effect in lateral direction is important for subthreshold characteristics when the effective channel length of DG-MOSFET is less than 10nm, Also, ballistic transport is setting important. This study shows modeling and design issues of nanoscale DG-MOSFET considering the 2D quantum effect and ballistic transport. We have optimized device characteristics of DG-MOSFET using a proper value of $t_{si}$ underlap and lateral doping gradient.

• Journal of IKEEE
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• v.11 no.3
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• pp.95-99
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• 2007

In this study, the electrical characteristics of Symmetric and Asymmetric High Voltage MOSFET(HV-MOSFET) under high temperature were investigated. And, the specific on-resistance, threshold voltage, transconductance, drain current of the HV-MOSFETs were measured over a temperatures range of 300K ${\leq}$ T ${\leq}$400K. From the result of measured data, specific on-resistance increases slightly with increasing temperature. Especially, at high temperature(at 400K) specific on-resistance was increased about 30% than that in room temperature. And, in high temperature condition (at 400K), drain current was decreased about 30%, Also, transconductance(gm) was decreases with increasing temperature.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.1-6
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• 2012

This paper presents the extraction and analysis of small-signal parameters of tunneling field-effect transistors (TFETs) by using TCAD device simulation. The channel lengths ($L_G$) of the simulated devices varies from 50 nm to 100 nm. The parameter extraction for TFETs have been performed by quasi-static small-signal model of conventional MOSFETs. The small-signal parameters of TFETs with different channel lengths were extracted according to gate bias voltage. The $L_G$-dependency of the effective gate resistance, transconductance, source-drain conductance, and gate capacitance are different with those of conventional MOSFET. The $f_T$ of TFETs is inverely proportional not to $L_G{^2}$ but to $L_G$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.4
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• pp.43-48
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• 1981

The Cdse TFTs with SiO gate insulator layer have been fabricated with vacum evaporatim technique. The effects of semiconductor thickness and drain-source channel length on the electrical propertis have been investigated. The TFTs with 1000$\AA$ SiO insulator, 1500 $\AA$ CdSe semiconductor layer and 40$\mu$m chammel length showed the best characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.9
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• pp.863-871
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• 2004

In this paper, we propose a subspace channel estimation technique for DS/CDMA DMB down link system, which can obtain reduction in numerical complexity by using of matched filtering outputs. The complexity reduction is considerable when the channel length is small and the system is moderately loaded. Previously proposed subspace-based blind channel estimation algorithm suffer from high numerical complexity for systems with large spreading gains. Although the proposed algerian suffers a slight performance loss, it becomes negligible for large observation length. Performance is evaluated through simulations and the derivation of the analytical MSE.