• Journal of the Institute of Convergence Signal Processing
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• v.13 no.4
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• pp.201-206
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• 2012

The indirect-contact ECG measurement is a newly developed method for unconstrained and nonconscious measurement in daily life. This study introduced a new method of electrode circuit design developed for reducing the 60Hz power line noise observed at the indirect-contact ECG measurement. By the introduced common-mode-driven shielding, the voltage of the electrical shield surrounding the capacitive coupling electrode is maintained at the same as the common mode voltage. Though the method cannot reduce the level of common mode voltage itself, that reduces effectively the differential mode noise converted from the common mode voltage by the difference of cloth impedance between the two capacitive coupling electrode. The experiment results using the actual indirect-contact ECG showed that the 60Hz power line noise was reduced remarkably though the reduction ratio was smaller than the expected by the theory. Especially, the reduction ratio became large for the large difference of cloth. It is expected that the introduced method is useful for reducing the power line noise under condition of poor electrical grounding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.493-502
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• 2001

This paper propose a new built-in current sensor(BICS) for current testing that has some advantages compared with conventional logic testing. The designed BICS detects the fault in circuit under test (CUT) and makes a Pass/Fail signal by comparison between CUT current and duplicated inverter current. The proposed circuit consists of a differential amplifier, a comparator and a inverter. It requires 10 MOSFETs and 3 inverters. Since the designed BICS do not require the extra clock, the added extra pin is only one output pin. The mode selection is not used in this circuit. Therefore we can apply the circuit to on-line testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When CUT is a 8$\times$8 parallel multiplier, area overhead of the BICS is about 4.34%.

• Journal of IKEEE
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• v.26 no.4
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• pp.714-721
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• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.5
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• pp.777-784
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• 2023

A sense amplifier is an essential peripheral circuit for designing a memory and is used to sense a small differential input signal and amplify it into digital signal. In this paper, a high-speed sense amplifier applicable to in-memory computing circuits is proposed. The proposed circuit reduces sense delay time through transistor Mtail that provides an additional discharge path and improves the circuit performance of the sense amplifier by applying m-GDI (: modified Gate Diffusion Input). Compared with previous structure, the sense delay time was reduced by 16.82%, the PDP(: Power Delay Product) by 17.23%, the EDP(: Energy Delay Product) by 31.1%. The proposed circuit was implemented using TSMC's 65nm CMOS process, while its feasibility was verified through SPECTRE simulation in this study.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.107-114
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• 2004

This paper presents block and timing diagrams of the DWA(Data Weighted Averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the MATLAB modeling, the optimized coefficients of the integrators are obtained to design the modulator. The fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed third-order multibit modulator is fabricated in a 0.35${\mu}{\textrm}{m}$ CMOS process. The modulator achieves 75dB signal-to-noise ratio and 74dB dynamic range at 1.2Vp-p 825kHz input signal and 52.8MHE sampling frequency.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.5
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• pp.52-58
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• 2001

In this paper, the low voltage linear tunable transconductors using the series composite transistor are presented. Due to the series composite transistor operating in the saturation region and the triode region, the proposed circuits have wide input range at low supply voltage. The designed transconductors have been simulated by HSPICE using $0.25{\mu}m$ n-welll CMOS process. Simulation results show that the cutoff frequency is 309M Hz and the THD of less than 1.1% can be obtained for the differential input signal of up to l.5VP-P with the input signal frequency of l0MHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.10-17
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• 1999

In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.1-9
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• 2000

This paper presents the error performance of 16 star-QAM with diversity reception in microcell systems in the presence of additive white Gaussian noise(AWGN) and cochannel interference. The differential detection of 16 star-QAM is split into phase detection and amplitude detection. This technique can reduce the degradation of error performance which is due to fading and the complexity of receiver. Diversity reception is proposed to improve the degradation of error performance due to fading. Equal gain and maximal ratio combinings were adopted for the phase detection and the amplitude detection, respectively. The performance of 16 star-QAM was evaluated for various of Rician factor K, maximum Doppler frequency f_DT, signal to cochannel interference ratio and diversity branch L.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.83-91
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• 1990

VOC(coltage controlled oscillator) circuits are necessary in applications such at the demodul-ation of FM signals, frequency synthesizer, and for clock recovery from digital data. In this paper, we designed the VCO circuit based on a OTA(operational transconductance amplifier) and the OP amp which using a differential amplifier by BiCMOS circuit. It consists of a OTA, voltage contorolled integrator and a schmitt trigger. Conventional VCO circuits are designed using the CMOS circuit, but in this paper we designed newly BiCMOS VCO circuit which has a good drive avlity, As a result of SPICE simulation, output frequency is 141KHz at 105KHz, and sensitivity is 15KHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.263-279
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• 1989

In part-1 of this paper, the error rate equations of digitally modulated signals transmitted though the Gaussian/Impulsive noise channel have been derived. Using the derived equations for the error probabilities of ASK, QAM, CPSK, DPSK, FSK and MSK signals, the error rate performances of digital modulation systems have been evaluated and represented in the figures as the functions of carrier-to-noise power ratio(CNR), impulsive index, and the ration of Gaussian noise power component to impulsive noise power component. The results are shown in graphs to known how much impulsive noise effects on digital signals than Gaussian noise.