• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.290-297
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• 2014

The synchronization of OFDM receiver is consisted of symbol timing offset(STO) estimation in time domain and carrier frequency offset(CFO) estimation in frequency domain. This paper proposes new algorithm for correcting the integer CFO after we have done correcting the STO and partial CFO. ICFO must be corrected, since the ICFO lead to degrade bit error rate(BER) of demodulation performance. The PN sequence has information which is subcarrier order since the modified PN sequence, length is same subcarrier, is used in this paper and is modulated each subcarrier by each chip. Thus the receiver track phase of PN sequence after FFTin order to find the subcarrier frequency offset. The proposed algorithm is faster and more simple than convenient methode as measuring carrier energy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.26-33
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• 2002

In this paper, a new four-quadrant MOS analog multiplier Is proposed using the quarter-square technique, which is based on the quadratic characteristics of MOS transistor operating in the saturation region and the difference operation of a source-coupled differential circuits. The proposed circuit has been fabricated in a p-well CMOS process. The multiplier achieves a total harmonic distortion of less than 1 percent for the both input ranges of 50 percent of power supply, a -3㏈ bandwidth of 30㎒ a dynamic range of 81㏈ and a power consumption of 40㎽. The active chip area is 0.54㎟. The supposed multiplier circuit is simple and adjust high frequency application because one input signal transfer output by one transistor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1C
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• pp.81-89
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• 2009

We propose a D-ATR UWB (Differential-Average Transmitted Reference Ultra Wide Band) system based on impulse radio. The TR-UWB systems including traditional TR (Transmitted Reference) and ATR (Average TR), exhibit a problem of reduced data rate, since reference signals are additionally transmitted. To tackle this issue, the transmitter of the proposed D-ATR system employs a differential coding like the conventional D-TR system. In addition, the receiver of the proposed system has the structure that can improve signal-to-noise ratio of the reference template used in the correlation process, by recursively averaging the received reference signals like the conventional ATR system. The simulation results in the IEEE 802.15.4a UWB multipath channel models reveal that the proposed D-ATR system achieves much better bit error rate performance as compared to the conventional D- TR system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.826-832
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• 2004

A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.

• Journal of IKEEE
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• v.22 no.4
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• pp.1218-1221
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• 2018

This paper presents a low-power 0.6-V 10-bit 200-kS/s double rail-to-rail successive approximation register (SAR) analog-to-digital converter (ADC). The proposed scheme allows input signal with 4 times power which is compared with conventional one by applying proposed rail-to-rail scheme, and that improves signal-to-noise ratio(SNR) of NTV SAR ADCs. The prototype was designed using 65-nm CMOS technology. At a 0.6-V supply and $2.4-V_{pp}$ (differential) and 200-kS/s, the ADC achieves an SNDR of 59.87 dB and consumes 364.5-nW. The ADC core occupies an active area of only $84{\times}100{\mu}m^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1C
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• pp.120-130
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• 2009

In this paper, we propose a receiver structure for frequency synchronization in OFDMA (Orthogonal Frequency Division Multiple Access) system which is considered as 3GPP LTE(Long Term Evolution) downlink. In general, OFDMA frequency synchronization consists of two parts: coarse synchronization and fine synchronization. We consider P-SCH (Primary-Synchronization Channel) and CP (Cyclic Prefix) of OFDMA symbol for coarse synchronization and fine synchronization, respectively. The P-SCH signal has two remarkable disadvantages that it does not have sufficiently many sub-carriers and its differential correlation characteristic is not good due to ZC (Zadoff Chu) sequence-specific property. Hence, conventional frequency synchronization algorithms cannot obtain satisfactory performance gain. In this paper, we propose a modified differential correlation algorithm to improve performance of the coarse frequency synchronization. Also, we introduce an effective PLL (Phase Locked Loop) structure to guarantee stable performance of the fine frequency synchronization. Simulation results verify that the proposed algorithm has superior performance to the conventional algorithms and the 2nd-order PLL is effective to track the fine frequency offset even in high mobility.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.12
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• pp.1084-1096
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• 2016

This paper presents method of design and analysis of a high-speed serial interface connector with a data rate of 12.5 Gbps. A high-speed serial interface connector is composed of various material and complex structures. It is very difficult to match the impedance of each discontinuous portion of connector. Therefore, this paper proposes the structure of a connector line that be simplified a connector. In the structure of proposed connector line, this research presents a method for extracting R, L, C and G parameters, analyzing the differential mode impedance, and minimizing the impedance discontinuity using time domain transmissometry and time domain reflectometry. This paper applies the proposed methods in the connector line to the high-speed serial interface connector. The proposed high-speed serial interface connector, which consists of forty-four pins, is analyzed signal transmission characteristics by changing the width and spacing of the four pins. According to the analysis result, as the width of the ground pin increases, the impedance decreases slightly. And as the distance between the ground pin and the signal pin increases, the impedance increases. In addition, as the width of the signal pin increases, the impedance decreases. And as the distance between the signal pin and the signal pin increases, the impedance decreases. The impedance characteristic of initial connector presents ranges from 96 to $139{\Omega}$. Impedance characteristic after applying the structure of proposed connector is shown as a value between 92.6 to $107.5{\Omega}$. This value satisfies the design objective $100{\Omega}{\pm}10%$.

• Journal of the Korean Society for Nondestructive Testing
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• v.16 no.1
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• pp.29-33
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• 1996

The eddy current test(ECT) probe of differential encircling coil type was designed and fabricated, and the optimum condition of ECT was derived for the examination of the irradiated fuel rod. The correlation between ECT test frequency and phase & amplitude was derived by performing the test of the standard rig that includes inner notches, outer notches and through-holes. The defect of through-hole was predicted by ECT at the G33-N2 fuel rod irradiated in the Kori-1 nuclear power reactor. The metallographic examination on the G33-N2 fuel rod was Performed at the defect location predicted by ECT. The result of metallographic examination for the G33-N2 fuel rod was in good agreement with that of ECT. This proves that the evaluation for integrity of irradiated fuel rod by ECT is reliable.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.26-34
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• 2007

This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.10-15
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• 2006

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.