• Journal of the Korea Society of Computer and Information
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• 제5권4호
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• pp.62-68
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• 2000

It was designed a high-speed analog input card that is a important device of ultrasonic testing flaw detector in the middle of non-destructive testing in this Paper. The A/D Board is inquired high-speed sampling rate and fast data acquisition system. This pater shows a design that has a function of Peak- Detection for ultrasonic testing by ISA Bus type and a 50MHz of A/D converter in order to do sampling more than quadruple frequency of transducer frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제27권2호
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• pp.115-122
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• 2016

In this paper, wideband Ku-band downconverter was designed to receiver digital satellite broadcasting. The low-nose downconverter was designed to form four local oscillator frequencies(9.75, 10, 10.75 and 11.3 GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75 GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select intermediate frequency bands by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64 dB, and the noise figure of low-noise amplifier was 0.7 dB, the P1dB of output signal 15 dBm, and the phase noise -85 dBc@10kHz at the band 1 carrier frequency of 9.75 GHz. The low noise block downconverter(LNB) for wideband digital satellite broadcasting designed in this paper can be used for global satellite broadcasting LNB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제27권9호
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• pp.825-833
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• 2016

This paper introduces a direct-conversion CMOS RF transmitter for the IEEE 802.15.4 standard with a low-power high-gain up-conversion mixer designed in $0.18{\mu}m$ process. The designed RF DCT(Direct Conversion Transmitter) is composed of differential DAC(Digital to Analog Converter), passive low-pass filter, quadrature active mixer and drive amplifier. The most important characteristic in designing RF DCT is to satisfy the 2.4 GHz Zigbee standard in low power. The quadrature active mixer inside the proposed RF DCT provides enough high gain as well as sufficient linearity using a gain boosting technique. The measurement results for the proposed transmitter show very low power consumption of 7.8 mA, output power more than 0 dBm and ACPR (Adjacent Channel Power Ratio) of -30 dBc.

• The Journal of the Korea institute of electronic communication sciences
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• 제9권10호
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• pp.1181-1187
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• 2014

In this paper, we implemented polar transmitt converter based on software for next generation digital wireless communication system. The implemented converter converted from rectangular to polar by CORDIC algorithm, and be made up of sweep for DDS output frequency using software control. The implemented converter shows can frequency control up to 1.16GHz within DDS frequency control range by software control. it means that transmitter can be control of varied blocks such as gain, phase, output and etc.. The implemented converter can be applied digital wireless communication system based on SDR.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제26권10B호
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• pp.1464-1469
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• 2001

본 논문에서는 디지털 하이브리드 위상고정루프(Digital Hybrid Phase-Locked Loop, DHPLL) 주파수 합성기 구조에서 고 순도 스펙트럼과 초고속 스위칭 속도를 위한 설계기술을 제안한다. D/A 변환기 출력으로 전압제어발진기(Voltage Controlled Oscillator, VCO)를 구동하는 개 루프(open-loop) 구성 방식과 기존 위상고정루프(Phase Locked Loop, PLL)의 폐 루프(closed-loop) 구성 방식을 혼합한 하이브리드 구조의 주파수 합성기를 고려하여, 시스템 변수(개 루프 대역과 위상 여유)와 성능 파라미터(정착시간, 위상 잡음, 그리고 최대 오버슈트(Max. overshoot)의 관계를 연구하였다. 그리고 이 관계를 통해 스펙트럼 순도와 스위칭 속도를 향상시키기 위한 최적의 3가지 설계방안을 제시한다. 컴퓨터 시뮬레이션 결과, 주파수 스위칭 과정에서 발생하는 최대 오버슈트가 0.0991%이고 완전 정상상태 도달시간은 0.288msec이다. offset 주파수 10KHz에서 위상 잡음은 -128.15dBc이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제19권1호
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• Proceedings of the Korea Contents Association Conference
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• 한국콘텐츠학회 2004년도 춘계 종합학술대회 논문집
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• pp.372-376
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• 2004

Digital memory circuits have been developed very fast according to the progress of semiconductor technology But It was very difficult to memorize a high frequency radio signal. Many years ago an analog loop was used for store of radio frequency signal, and the digital radio frequency memory was made to the development of wideband amplifier and high speed sampler. We present a design of wide-band DRFM using Johnson code and the simulation results with respect to the sampling speed. in this paper.

• Journal of the Korea Academia-Industrial cooperation Society
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• 제6권5호
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• pp.401-406
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• 2005

Digital memory circuits have been developed very fast according to the progress of semiconductor technology. But it was very difficult to memorize a wideband radio frequency signals. Many years ago, an analog frequency memory loop(FML) was used for store of radio frequency signal and the digital radio frequency memory was made according to the development of wideband amplifier and high speed sampler. We present a design of wideband digital radio frequency reproduction device using ladder circuit and the simulation results with respect to the sampling speed in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.365-367
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• 2013

본 논문에서는 $0.18{\mu}m$ CMOS 공정 기술을 이용하여 12-bit 1MSps 연속 근사화 아날로그-디지털 변환기(Analog to Digital Converter : ADC)를 설계하였다. 설계된 아날로그-디지털 변환기는 Cadence Tool을 이용하여 시뮬레이션 및 레이아웃을 진행하였다. 시뮬레이션 결과 1.8V의 공급전압에서 전력 소모는 5.5mW였고, 입력 신호의 주파수가 100kHz일 때, SNDR은 70.03dB, 유효 비트수는 11.34bit의 결과를 보였다. 설계된 변환기는 $0.8mm{\times}0.7mm$ 크기로 레이아웃 되었다.

• Journal of Sensor Science and Technology
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• 제10권2호
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• pp.142-147
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• 2001

Using transmission-line equivalent circuit based on cross-field model for an interdigital acoustic wave transducer, an efficient simulation technique of SAW filters by SPICE is proposed. Propagation of surface acoustic wave is modeled as transmission line so that frequency-dependent circuit elements are not needed in the equivalent circuit of an interdigital transducer. Because the equivalent circuits for frequency-dependent circuit elements are not derived approximately, and a small number of circuit elements are used in the equivalent circuit for filters, simulation time is much reduced. The utility of the proposed technique is demonstrated through simulation for the characteristics of SAW filters such as insertion loss, input admittance, passband ripple, and harmonic frequency response.