• Journal of Advanced Marine Engineering and Technology
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• v.38 no.1
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• pp.48-55
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• 2014

These Xenon flashlamp power supply for Ultra Violet has converter with high voltage conversion ratio. General model is composed of transformer with high voltage conversion ratio and voltage doubler rectifier circuit. Purpose of power supply leads dielectric breakdown of Xenon flashlamp and passes current rapidly. When passing current, it has to limit current to avoid over-heat, damage of electrode and acceleration of gas oxidation which are cause of performance degradation of lamps. Generally, inductors and resistors, which are called as "Ballast," are used to limit currents. Generally, Transformer has high turn ratio to make high voltages. But we can get high voltages using the transformer with low turn ratio which is driven with self resonance. Also, an advantage of self resonance is to make a circuit simply through impedance of transformer in resonance frequency which filters output voltage. As using an unique impedance of transformer, the circuit does not need other impedance elements like the ballast. So the power supply assures high efficiency of the arc discharge.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.685-690
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• 2013

This paper has proposed a multi-channel and wide gain-range baseband circuit blocks for the IEEE 802.15.4g MR-OFDM SUN systems. The proposed baseband circuit blocks consist of two negative-feedback VGAs, an active-RC 5th-order chebyshev low-pass-filter, and a DC-offset cancellation circuit. The proposed baseband circuit blocks provide 1 dB cut-off frequencies of 100 kHz, 200 kHz, 400 kHz, and 600 kHz respectively, and achieve a wide gain-range of +7 dB~+84 dB with 1 dB step. In addition, a DC-offset cancellation circuit has been adopted to mitigate DC-offset problems in direct-conversion receiver. Simulation results show a maximum input differential voltage of $1.5V_{pp}$ and noise figure of 42 dB and 37.6 dB at 5 kHz and 500 kHz, respectively. The proposed I-and Q-path baseband circuits have been implemented in $0.18-{\mu}m$ CMOS technology and consume 17 mW from a 1.8 V supply voltage.

• Food Engineering Progress
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• v.15 no.4
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• pp.398-403
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• 2011

A dielectric barrier discharge plasma (DBDP) treatment system was fabricated and the optimum operating conditions for the plasma generation were determined in order to explore the potential of cold plasma as a non-thermal proessing technology. The microbial inactivation performance of the system was also evaluated against Staphyloocus aureus. The system consisted of power supply, transformer, electrode assembly and sample treatment plate. The input power was 220 V single phase AC and amplified to 10.0-50.0 kV on a transformer. A pulsed sine wave of frequency 10.0-50.0 kHz was introduced to the electrode embedded in ceramic as a dielectric barrier material in order to generate plasma at atmospheric pressure. Higher currents and consequently greater power were required for the plasma generation as the frequencies increased. A homogeneous and stable plasma was generated at currents of 1.0-2.0, and frequencies of 32.0-35.3 kHz. The optimum electrode-gaps for the plasma generation were 1.85 mm without loaded samples. More power was consumed as the electrode-gaps increased. The practically optimum electrode- gap was, however, 2.65 mm when samples were treated on slide-glasses for microbial inactivation. The maximum temperature increase after 10 min treatment was less than 20$^{\circ}C$, indicating no microbial inactivation effect by heat and thereby insuring a non-thermal method. The DBDP inactivation effect against Staphyloocus aureus increased linearly with treatment time up to 5 min, but plateaued afterward. More than 5 log reduction was achieved by 10 min treatment at 1.25 A.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of Sensor Science and Technology
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• v.7 no.3
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• pp.154-162
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• 1998

A planar Bi-Sb multijunction thermal converter with high thermal sensitivity and small ac-dc transfer error has been fabricated by preparing the bifilar thin film Pt-heater and the hot junctions of thin film Bi-Sb thermopile on the $Si_{3}N_{4}/SiO_{2}/Si_{3}N_{4}$-diaphragm, which functions as a thermal isolation layer, and the cold junctions on the dielectric membrane supported with the Si-substrate, which acts as a heat sink, and its ac-dc transfer characteristics were investigated with the fast reversed dc method. The respective thermal sensitivities of the converter with single bifilar heater were about 10.1 mV/mW and 14.8 mV/mW in the air and vacuum, and those of the converter with dual bifilar heater were about 5.1 mV/mW and 7.6 mV/mW, and about 5.3 mV/mW and 7.8 mV/mW in the air and vacuum for the inputs of inside and outside heaters, indicating that the thermal sensitivities in the vacuum, where there is rarely thermal loss caused by gas, are higher than those in the air. The ac-dc voltage and current transfer difference ranges of the converter with single bifilar heater were about ${\pm}1.80\;ppm$ and ${\pm}0.58\;ppm$, and those of the converter with dual bifilar heater were about ${\pm}0.63\;ppm$ and ${\pm}0.25\;ppm$, and about ${\pm}0.53\;ppm$ and ${\pm}0.27\;ppm$, respectively, for the inputs of inside and outside heaters, in the frequency range below 10 kHz and in the air.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.2
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• pp.205-213
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• 2002

This paper deals with the implementation of three-phase VSI systems which can control the power regenerated from DC bus line to AC supply. The overall system consists of the line-to-line voltage and line current sensors, an actual power calculator using d-q transformation method, a complex power controller with PI control scheme, a gating signal generator for modified ｑ-conduction mode, a DPLL for frequency followup, and Power circuits. Control board is constructed by using a 32-bit DSP TMS32C32, two EFLDs , six ADCs, and a DAC. To verify the performance of the proposed system, we designed and constructed the propotype with the power rating of 5kVA at AC 220V. Experimental results show that the regenerated active power is well controlled to its command vague and the regenerated reactive power still remained at nearly zero through all operating modes.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.3
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• pp.377-383
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• 2012

In this paper, a new design of a planar rectenna system and its application to a wake-up receiver operating for incoming signal with a specified frequency are proposed for low-power sensor system applications. The planar and integrable rectenna system is designed with DGSs(Defected Ground Structures) at 2.4 GHz. The DGSs reject harmonic components of 4.8 and 7.2 GHz and eliminate 2.4 GHz fundamental frequency for DC-path filtering. The rectenna system has been evaluated for the conversion output voltages, and applied to the switching of a power supply at the low-power sensor receivers. The proposed system has been evaluated for the wake-up performance by testing a lownoise amplifier operation. From the experimental results, the proposed receiver system presents excellent operation performances.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.43-51
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• 2013

This paper presents a design and implementation of a low power switched-capacitor 3rd-order delta-sigma modulator for a digital hearing-aid application. The power consumption is reduced by minimizing the output swing of integrators through optimizing the coefficients of modulator architecture and using class-AB output operational amplifiers. The modulator was implemented in a 130nm CMOS technology, and measured to have 79dB of SNR(Signal-to-Noise Ratio) in the signal bandwidth between 100Hz and 10kHz with an oversampling ratio of 160. The power consumption was $60{\mu}W$ from 1.2V power supply and the modulator core occupied $0.53mm{\times}0.53mm$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.12
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• pp.4984-4990
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• 2010

In this paper, a Step-down CMOS DC-DC Converter using low power switched capacitor method is designed in a 0.5 ${\mu}m$ technology for the integration of devices. Conventional DC-DC converter is used inductor that can store energy in a magnetic field but have low efficiency because power consumption is caused by magnetic flux. And there were problems with size, weight and price to integrate chip. In this paper, a proposed Inductorless step-down CMOS DC-DC converter of low power using SC method is designed in a 0.5um technology to solve these problems. Designed DC-DC converter have 96% power efficiency with 200kHz frequency by using cadence simulation.