• Proceedings of the Korea Information Processing Society Conference
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• 2022.11a
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• pp.27-29
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• 2022

최근 인공지능 애플리케이션이 많이 사용되고 이러한 애플리케이션에서 데이터 희소성이 높아지고 있어 이러한 희소 데이터를 효율적으로 처리하기 위한 하드웨어 구조들이 많이 소개되고 있다. 본 논문에서는 희소 데이터 처리 시 전력 소모량을 낮출 수 있는 새로운 하드웨어 구조를 제안한다. 일반적인 인공지능 하드웨어에서 많이 사용되는 시스톨릭 어레이 구조를 기반으로 하며, 제안된 저전력 PE 가 희소 데이터 처리시 희소하지 않은 데이터 처리 시보다 최대 2 배의 전력 소모량을 줄일 수 있는 것으로 나타났다.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.05a
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• pp.203-205
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• 2023

최근 성장하고 있는 드론 산업에 맞추어 전세계적으로 드론 운용을 위한 식별 및 인증 규정을 마련하고 있는 추세이다. 대표적으로, 미국 FAA 에서 채택한 Remote ID 기반의 식별방식이 있다. 그러나, ID 기반의 인증 방식은 해당 ID 가 탈취 혹은 위조될 경우 다른 드론으로 위장하여 여러 심각한 사회 문제를 일으킬 위험성이 있다. 따라서 드론에 탑재된 여러 센서나 모터와 같은 하드웨어의 고유한 특성을 이용하여 Remote ID 를 대체하거나 이중 인증에 이용하려는 연구가 이루어지고 있다. 본 논문에서는 드론에 탑재된 하드웨어의 고유특성을 이용한 다양한 식별 및 인증시스템에 대한 연구에 대하여 살펴본다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.3
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• pp.175-182
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• 2004

There is a growing interest in speaker verification, which verifies someone by his/her voices. There are many speaker vitrification algorithms such as HMM and DTW. However, it is impossible to apply these algorithms to memory limited applications because of large number of feature vectors to register or verify users. In this paper we introduces a speaker verification system using SVM, which needs a little memory usage and computation time. Also we proposed hardware architecture for SVM. Experiments were conducted with Korean database which consists of four-digit strings. Although the error rate of SVM is slightly higher than that of HMM, SVM required much less computation time and small model size.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.74-80
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• 2012

Recently at SCIS2011, Nakatsu et. al. proposed multi-round Correlation Power Analysis(CPA) on Hardware Advanced Encryption Standard(AES) to improve the performance of CPA with limited number of traces. In this paper, we propose, Multi-Round CPA to retrieve master key using CPA of 1round and 2round on Hardware DES. From the simulation result for the proposed attack method, we could extract 56-bit master key using the 300 power traces of Hardware DES in DPA contes. And it was proved that we can search more master key using multi-round CPA than using single round CPA in limited environments.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.112-118
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• 2014

As higher quality of image is required for digital image scaling, longer processing time is required. Therefore the technology that can make higher quality image quickly is needed. We propose the double linear-cubic convolution interpolation which creates the high quality image with low complexity and hardware resources. The proposed interpolation methods which are made up of four one-dimensional linear interpolations and one one-dimensional cubic convolution perform linear-cubic convolution interpolation in horizontal and vertical direction. When compared in aspects of peak signal-to-noise ratio(PSNR), performance time and amount of hardware resources, the proposed interpolation provided better PSNR, low complexity and less hardware resources than bicubic convolution interpolation.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.80-86
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• 2002

This paper presents a fast hardware architecture to implement a 2-D DWT(Discrete Wavelet Transform) computed by lifting scheme framework. The conventional 2-D DWT hardware architecture has problem in internal memory, hardware resource, and latency. The proposed architecture was based on the 4-way partitioned data set. This architecture is configured with a pipelining parallel architecture for 4-way partitioning method. Due to the use of this architecture, total latency was improved by 50%, and memory size was reduced by using lifting scheme.

• Journal of IKEEE
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• v.24 no.2
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• pp.502-506
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• 2020

With the development of autonomous driving technology, the importance of object recognition technology is increasing. Haze removal is required because the hazy weather reduces visibility and detectability in object recognition. However, the image from which the haze has been removed cannot properly reflect the unique color, and a detection error occurs. In this paper, we use CIE1931 color coordinate system to extend or reduce the color area to provide algorithms and hardware that reflect the colors of the real world. In addition, we will implement hardware capable of real-time processing in a 4K environment as the image media develops. This hardware was written in Verilog and implemented on the SoC verification board.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.153-160
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• 1996

In this paper, we propose an efficient digital architecture for the discrete-time cellular neural networks (DTCNN's). DTCNN's have the locality and the translation invariance in the templates which determine the patterns of the connection between the cells. Using distributed arithmetic (DA) and the characteristics of DTCNN, we propose a simple implementation of DTCNN. The bus width in the cell-to-cell interconnection is reduced to one bit because of DA's bitwise operation. We implemented the reconfigurable architecture of DTCNN using programmable FPGA.

• Journal of IKEEE
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• v.24 no.1
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• pp.186-193
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• 2020

In this paper, we propose a multi-threading system to support reconfigurable hardware accelerators on Zynq SoC. We implement high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators to achieve maximum performance available on the platform. In this system, up to four reconfigurable hardware accelerators synchronized with SW threads can be dynamically reconfigured to provide adaptive computing capabilities according to the given image resolution and the compression ratio. JPEG decoding is operated using images with resolutions 480p, 720p, 1080p at the compression ratio of 7:1-109:1. We show that significant performance improvements are achieved as the image resolution or the compression ratio increase. For 1080p resolution, the performance improvement is up to 79.11 times with throughput speed of 99 fps at the compression ratio 17:1.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.577-586
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• 2011

This paper describes the development of hardware simulator for the operation analysis of DC microgrid. The hardware simulator consists of several distributed power sources such as a wind power generation, solar power and fuel cell, and two energy storages such as a supercapacitor and battery. The main controller which performs a role of energy management and state monitoring is connected with the local controller in each power source and storage through ethernet-based communication link. The developed hardware simulator can be utilized to analyze the performance DC microgrid with practical manner.