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http://dx.doi.org/10.5573/ieie.2014.51.3.112

VLSI Architecture of Digital Image Scaler Combining Linear Interpolation and Cubic Convolution Interpolation  

Moon, Hae Min (Dept. of Information and Communication Engineering, Chosun University)
Pan, Sung Bum (Dept. of Electronics Engineering, Chosun University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.3, 2014 , pp. 112-118 More about this Journal
Abstract
As higher quality of image is required for digital image scaling, longer processing time is required. Therefore the technology that can make higher quality image quickly is needed. We propose the double linear-cubic convolution interpolation which creates the high quality image with low complexity and hardware resources. The proposed interpolation methods which are made up of four one-dimensional linear interpolations and one one-dimensional cubic convolution perform linear-cubic convolution interpolation in horizontal and vertical direction. When compared in aspects of peak signal-to-noise ratio(PSNR), performance time and amount of hardware resources, the proposed interpolation provided better PSNR, low complexity and less hardware resources than bicubic convolution interpolation.
Keywords
Bilinear; Bicubic convolution; Interpolation; Image Scaling; VLSI;
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Times Cited By KSCI : 2  (Citation Analysis)
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