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A Hardware Implementation of Support Vector Machines for Speaker Verification System  

최우용 (한국전자통신연구원 정보보호연구단)
황병희 (부산대학교 컴퓨터공학)
이경희 (부산대학교 컴퓨터공학)
반성범 (한국전자통신연구원 정보보호연구)
정용화 (고려대학교 컴퓨터공학)
정상화 (부산대학교 컴퓨터공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SP / v.41, no.3, 2004 , pp. 175-182 More about this Journal
Abstract
There is a growing interest in speaker verification, which verifies someone by his/her voices. There are many speaker vitrification algorithms such as HMM and DTW. However, it is impossible to apply these algorithms to memory limited applications because of large number of feature vectors to register or verify users. In this paper we introduces a speaker verification system using SVM, which needs a little memory usage and computation time. Also we proposed hardware architecture for SVM. Experiments were conducted with Korean database which consists of four-digit strings. Although the error rate of SVM is slightly higher than that of HMM, SVM required much less computation time and small model size.
Keywords
SVM;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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