• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.7
• /
• pp.89-95
• /
• 2014

An LED lighting which adjusted brightness according to the surround ambient implemented using PWM technology and power devices. To measure the brightness of surround ambient a CdS sensor was used. A control board for the generation of the PWM signal was made using a MCU and duty ratio was controlled according to light intensity of surround ambient of the system. To drive the LED lamps which require high-voltage and high-current power devices were used for switching the DC power supply. Measurement results show that the IGBT is excellent as only lineality but the PowerBJT is more good to consider to efficiency and cost.

• Proceedings of the KIPE Conference
• /
• 2007.07a
• /
• pp.32-34
• /
• 2007

전자산업 부문의 친환경 대응이 이슈화 되면서 전자기기의 대기전력 소비감소를 위한 연구가 지속적으로 수행되고 있다. 전자기기의 대표적인 전원공급장치인 Switched Mode Power Supply(SMPS)의 경우 부하기기의 대기모드 시 극도로 낮은 출력전력에서 고효율을 달성해야 하는 요구가 높다. 특히 많은 SMPS들이 부하기기의 요구에 의하여 다출력 컨버터로 설계되어 있는데, 이러한 다출력 구조에서 대기모드 시 불필요한 출력을 절체함과 동시에 저전력에서 고효율을 내기가 쉽지 않다. 또한 다출력 구조로 인한 Cross Regulation 문제를 극복해야 하는 과제가 있다. 따라서 본 논문에서는 단일 컨버터 혹은 복수의 컨버터로 구성되어 있는 다출력 컨버터에서 대기전력 개선을 위한 Secondary Side Post Regulator(SSPR), 전류모드, Power Sequence 제어기술을 제안하고, 대기전력과 더불어 SSPR의 Cross Regulation 특성 개선을 검토하였다. 그리고 제안한 기술이 구현된 다출력 구조의 110W와 270W급 SMPS를 제작하여 회로의 타당성 및 우수성을 검증하였다.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.1
• /
• pp.50-54
• /
• 2010

A Container Security Device (CSD) which is different existing RFID Tag strengthens the physical security as mounted inside the container and the information security as encrypts doubly a data. CSD must use the resources efficiently in order to operate with the battery. Therefore, it needs low-power mechanism which repeats the sleep period and channel scan period. However, by adjusting these periods, the trade-off occurs between energy efficiency and network connectivity. In this paper, we implement low-power CSD and resolve this problem by adjusting beacon period and channel scan time. As a result, We guarantee the network connectivity 95% or more and maximum life up to 16 days using common AA batteries.

• Korean Journal of Optics and Photonics
• /
• v.3 no.3
• /
• pp.178-182
• /
• 1992

An air-cooled discharge-heated copper-vapor laser system with its inter-electrode distance of 45 cm has been developed by utilizing an alumina ceramic plasma tube of 1.6 cm in diameter and 50 cm in lengih. For operating the laser, a dc high voltage power supply with output rating of 6 kV and 500 mA, a resonant charging circuitry consisting partly of an 1.8 H inductor assembly and a 5 nF storage capacitor, and a thyratron driver operating up to 7 kHz have also been developed. The present laser system starts lasing at the tube temperature of about $1350^{\circ}C$ and an maximum average output power of 0.7 W has been obtained at 12 kV, 4.5 kHz. 50 mbar of Ne buffer gas pressure, and at the tube temperature of $1460^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.1
• /
• pp.75-82
• /
• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.4
• /
• pp.352-361
• /
• 2010

In this paper, a compact 20 W block-up-converter for C-band satellite communication is designed and implemented. The designed block up-converter consists of an intermediate frequency circuit, a mixer and local oscillator, a driver amplifier, a solid-state power amplifier, waveguide circuits, and a power supply module. To reduce the size of the block-up-converter, all circuits are assembled within an housing, so its dimension is just $21{\times}14{\times}11cm^3$. Especially, the waveguide filter and microstirp-to-waveguide transition are easily implemented using an housing. Also, to meet spurious and harmonics specification, various compact microstrip filters including an elliptic filter are integrated. Measurement results show that the developed block up-converter has good electrical performances: the output power of 43.7 dBm, the minimum gain of 65 dB, the gain flatness of ${\pm}1.84$, the IMD3 of -35 dBc, and the harmonic level of -105 dBc.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.5
• /
• pp.796-805
• /
• 2000

A 30GHz band low noise amplifier module, which has linear gain of 30dB and noise figure of 2.6dB, for 30GHz satellite communication transponder was developed by use of MMIC and thin film MIC technologies. Two kinds of MMIC circuits were used for the low noise amplifier module, the first one is ultra low noise MMIC circuit and the other is wideband and high gain MMIC circuit. The pHEMT technology with 0.15$mu extrm{m}$ of gate length was applied for MMIC fabrication. Thin film microstrip lines on alumina substrate were used to interconnect two MMIC chips, and the thick film bias circuit board were developed to provide the stabilized DC bias. The input interface of the low noise amplifier module was designed with waveguide type to receive the signal from antenna directly, and the output port was adopted with K-type coaxial connector for interface with the frequency converter module behind the low noise amplifier module. Space qualified manufacturing processes were applied to manufacture and assemble the low noise amplifier module, and space qualification level of environment tests including thermal and vibration test were performed for it. The developed low noise amplifier was measured to show 30dB of minimum gain, $\pm$0.3dB of gain flatness, and 2.6dB of maximum noise figure over the desired operating frequency range from 30 to 31 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.3
• /
• pp.517-526
• /
• 2008

A one-chip DC-DC converter circuit for OLED(Organic Light-Emitting Diode) display module of automotive clusters is newly proposed. OLED panel driving voltage circuit, which is a charge-pump type, has improved characteristics in miniaturization, low cost and EMI(Electro-Magnetic Interference) compared with DC-DC converter of PWM(Pulse Width Modulator) type. By using bulk-potential biasing circuit, charge loss due to parasitic PNP BJT formed in charge pumping, is prevented. In addition, the current dissipation in start-up circuit of band-gap reference voltage generator is reduced by 42% and the layout area of ring oscillator is reduced by using a logic voltage VLP in ring oscillator circuit using VDD supply voltage. The driving current of VDD, OLED driving voltage, is over 40mA, which is required in OLED panels. The test chip is being manufactured using $0.25{\mu}m$ high-voltage process and the layout area is $477{\mu}m{\times}653{\mu}m$.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.4
• /
• pp.43-51
• /
• 2013

This paper presents a design and implementation of a low power switched-capacitor 3rd-order delta-sigma modulator for a digital hearing-aid application. The power consumption is reduced by minimizing the output swing of integrators through optimizing the coefficients of modulator architecture and using class-AB output operational amplifiers. The modulator was implemented in a 130nm CMOS technology, and measured to have 79dB of SNR(Signal-to-Noise Ratio) in the signal bandwidth between 100Hz and 10kHz with an oversampling ratio of 160. The power consumption was $60{\mu}W$ from 1.2V power supply and the modulator core occupied $0.53mm{\times}0.53mm$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.3
• /
• pp.427-433
• /
• 2002

This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.