• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.20 no.1
• /
• pp.34-40
• /
• 2006

This paper proposed power system for new DC 49[V] telecommunication using forward three-phase PWM rectifier power factor and efficiency for improvement of ripple voltage. Proposed power system for DC 48[V] telecommunication that consists of power conversion devices including switch, inductor and condenser were made between each line, in power inverter device of each switch control turn-on in period of continuity time control to get power factor '1' of sine wave current and on-off of switch lessens peak current that was happened and got conversion efficiency 92.1[%] composing in PWM rectifier of forward form instead of general PWM rectifier. Also, harmonic input regulation value(IEC61000-3-2 Class-As) satisfy input current and reduce ripple factor of output voltage in state that distortion of three-phase supply is overlapped each other.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.10a
• /
• pp.285-288
• /
• 2012

Since the non-overlapping gate driver used in conventional DC-DC boost converters generates fixed dead-times, the converters suffer from the body-diode conduction loss or the charge-sharing loss. To reduce the efficiency degradation due to these losses, this paper presents a PWM DC-DC boost converter with adaptive dead-time control. In light loads, power switching is also employed to increase the efficiency. The designed DC-DC boost converter can thus achieve high efficiency at wide current range. The proposed DC-DC boost converter has 3.3V output from a 2.5V input with 0.18um technology. It operates at 500KHz and has a maximum power efficiency of 97.8%.

• Journal of Korea Society of Industrial Information Systems
• /
• v.8 no.2
• /
• pp.84-91
• /
• 2003

KOMPSAT series use software-controlled unregulated bus system in which the main bus is directly connected to a battery and the duty-ratio for PWM switch is controlled by the on-board satellite software. This paper proposes a new power-stage circuit that can be available for modularization of the power regulator which is used at the software-controlled unregulated bus system satellite. And we analyze the proposed power-stage operation according to its operating modes and verify it by performing software simulation and hardware experiment using prototype. We construct a parallel-module converter which is composed of proposed power-stages and perform experiment to verify modular characteristics of the proposed power-stage. Finally, we verify the usefulness of the proposed power-stage by comparing above results with those of a parallel-module converter made of conventional power-stages.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.1
• /
• pp.89-98
• /
• 2002

Optical current sensor and optical voltage sensor modules were designed and fabricated to improve measurement error and insulation in automatic power distributor By using Faraday effect, optical current sensor with an $\alpha$-iron core was designed and fabricated to minimize current induction of the other phase and was optimized to maintain linearity. Optical voltage sensor was fabricated owing to the pockets effect and adopted spatial electric field type because of small room in an automatic power distributor. To connect a distributor with an external terminal for signal processing, optical multi connector was designed, fabricated and tested for coupling loss and gas leakage. The linearity of optical current sensor for applied current maintains variation of smaller than 2.5% for applied current range from 20A to 700A. The linearity of optical voltage sensor was smaller than 1% for appling voltage from 6.6kV to 19.8kV. Since the measured characteristics are good, these devices can be considered as being applicable in practice.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.6
• /
• pp.408-420
• /
• 2003

This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.3 no.4
• /
• pp.287-297
• /
• 1998

RPWM(Random Pulse Width Modulation) is a switching technique to spread the voltage and current harmonics on wide frequency area. Using randomly changed switching frequency of the inverter, the power spectrum of the electromagnetic acoustic noise can be spread into the wide-band area. And the wide-band noise is much more comfortable and less annoying than the narrow-band one. So RPWM have been attracting an interest as an excellent reduction method of acoustic noise on the inverter drive system. In this paper a new RPPWM(Random Position PWM) is proposed and implemented. Each of three pulses is located randomly in each switching intervals. Along with the randomization of PWM pulses, the space vector modulation is processed on the C167 microcontroller also. The experimental results show that the voltage and current harmonics were spread into wide band area and that the audible switching noise was reduced by proposed RPPWM method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.11 s.353
• /
• pp.37-47
• /
• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.3
• /
• pp.69-76
• /
• 2008

This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.22 no.4
• /
• pp.587-593
• /
• 2021

Since 2017, a total of 29 fire accidents have occurred in energy storage systems (ESSs) as of June 2020. The common mode voltage (CMV) is one of the electrical hazards that is assumed to be a cause of those fire accidents. Several cases of CMV that violate the allowable insulation level of a battery section are being reported in actual ESS operation sites with △-Y winding connections. Thus, this paper evaluates the characteristics of CMV. An ESS site was modeled with an AC grid, PCS, and battery sections using PSCAD/EMTDC software. As a result of a simulation based on the proposed model, it was confirmed that characteristics of CMV vary significantly and are similar to actual measurements, depending on the grounding method of the internal transformer for PCS. The insulation level of the battery section may be severely degraded as the value of CMV exceeds the rated voltage in case of a grounding connection. It was found that the value of CMV dramatically declines when the internal transformer for PCS is operated as non-grounding connection, so it meets the standard insulation level.

• Proceedings of the KIPE Conference
• /
• 2018.07a
• /
• pp.165-167
• /
• 2018

본 논문은 다권선 변압기를 이용한 능동 셀 밸런싱 회로의 에너지 전달 효율을 향상시킬 수 있는 스위칭 방식을 제안한다. 다권선 변압기를 이용한 밸런싱 회로는 셀 당 하나의 스위치가 사용되며, 하나의 변압기 권선을 두 개의 셀이 공유하는 구조를 가져 다른 능동 셀 밸런싱 회로보다 소량의 능동 소자 및 수동 소자가 사용되는 장점을 갖는다. 이 밸런싱 회로는 직렬 셀 전압의 분포에 따라 에너지를 공급하는 소스 셀과 에너지를 받는 목표 셀을 선택하여 벅-부스트 및 플라이백 방식으로 동작한다. 하지만, 플라이백 동작에서 기존의 스위칭 방식을 사용할 경우, 변압기의 커플링 계수의 영향으로 인해 밸런싱 과정 중 비-목표 셀로 전달되는 에너지가 발생하게 된다. 이는 에너지 전달 효율을 감소시켜 셀 밸런싱 과정 중 새로운 셀 불균형 현상을 초래한다. 본 논문에서는 플라이백 동작에서 변압기의 커플링 영향을 최소화하여 셀 밸런싱을 효과적으로 수행할 수 있는 스위칭 방식을 제안하였다. 제안한 스위칭 방식의 성능은 1 W급 시작품을 이용한 실험을 통하여 검증되었다.