• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.369-372
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• 2000

본 논문에서는 P-HEMT Gate-바이어스 튜닝에 의한 위상동기 마이크로파 발진기를 설계하였다. 설계된 유전체 발진기는 병렬궤환공진 형태로서 P-HEMT의 게이트단에서 전압을 제어하여 전압제어발진기 형태로 주파수를 가변시키므로서 안정된 위상동기신호를 나타나도록 하였다. 위상동기방식은 외부에서 제공되는 125㎒의 기준주파수를 SRD로 체배시켜 하모닉 신호를 이용한 마이크로파 샘플링 위상검파 방식으로 설계하였으며, 유전체 발진기의 자유발진신호와 샘플링 신호사이의 위상비교에 의하여 ±1㎒ 범위의 고안정 특성을 갖는 13.25㎓대역의 위상고정 발진기의 동기화와 저 위상잡음을 나타내었다.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2005.05a
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• pp.914-921
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• 2005

신제품으로 개발 중인 초소형 CMOS RF 전압 제어발진기(VCO) IC 에 대한 공인된 시험 규격은 현재 개발되어 있지 않다. 또한 제조업체들은 고유의 시험방법을 보유하고 있을 것이나 공개하지 않고 있는 실정이다. 한편 일부 해외 제조업체에서 국제 규격인 IEC 또는 JEDEC 을 기준으로 시험방법을 제시하고 있지만, 이러한 시험규격들은 개별 부품을 솔더링하는 하이브리드 공정을 이용하여 제작된 VCO 를 대상으로 한 것이다. 그러므로 CMOS 반도체 공정을 이용한 IC 형으로 개발 중인 VCO 를 평가하기에는 적합하지 않다. 이에 본 연구에서는 신개발 부품인 CMOS RF VCO IC 에 대한 신뢰성 시험 및 평가 기준을 수립하고, 신뢰성 확보를 위한 신제품 개발 단계에서의 신뢰성 평가 프로세스를 개발하고자 한다.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.5
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• pp.756-761
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• 2009

In this paper, a X band voltage controlled oscillator is proposed. The oscillator uses a transistor as an oscillating element and its oscillating frequencies are controlled by the tuning voltage of varactor diode. Using the circuit simulation tools, the matching circuits between the transistor and varactor diode, its input and output matching circuits, and a feedback circuits are designed. The measured results of the fabricated oscillator show that its oscillation frequencies are from 10.50GHz to 10.88GHz according to the turning voltages of 1V to 18V, its output power levels are about 4.3dBm, and its phase noise is around -43.5dBc/Hz at 100kHz offset frequency of 10.5GHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.11
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• pp.1176-1183
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• 2003

In this paper, miniature voltage-controlled oscillator(VCO) for 1.6 ㎓ PCS band is designed and implemented using the LTCC technique. Circuit level design using commercial components is performed, and passive L, C elements embedded in LTCC substrate is optimized by simulation tools. Embedded passive components are modeled into equivalent circuits and their circuit parameters are extracted for circuit simulation. Utilizing the designed embedded passive elements and 21 layers LTCC substrate, VCO with 4.0${\times}$4.0${\times}$1.6 ㎣ dimensions is designed and fabricated. Developed VCO operates in 2.7 V with 8.5 ㎃ current consumption. The phase noise performance of VCO is below -112.61 ㏈c/㎐ at 100 ㎑ offset and harmonic suppression characteristics is measured above -30 ㏈.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.2
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• pp.124-132
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• 1987

In this paper, a new Open and Closed Loop Alternation(OCLA) frequency synthesizer is developed to eliminate a frequency error occurring in the transition state of a frequency hopping. This frequency synthesizer consists of a phase comparator(PC), two low pass filters(LPF), two voltage controlled oscillators(VCO), switching elements, a programmable divider and frequency hopping controller, and the stabilized output frequency can be obtained by switching performance. In addigion, it can be found that the characteristic of its circuit construction makes it easy to attach an external circuitry to the open loop.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.9
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• pp.1277-1283
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• 2013

In this paper, a novel voltage controlled oscillator(VCO) using CSRR loaded microstrip line for X-band RADAR is proposed. Using the microstrip line loaded CSRR inserted between the oscillator and buffer to the filter, the harmonic suppression has been improved. The measured results of the fabricated oscillator shows that its oscillation frequencies are from 9.28 to 9.39GHz according to the tuning voltage 0~10V, its output power level are about 16.6dBm at 9.35GHz. Compared with VCO using the conventional VCO, VCO using CSRR loaded microstirp, the harmonic suppression characteristic has been improved in 10.4dB

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.19-25
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• 2001

In this paper, the design and simulation results of IF frequency synthesizer section has been described. We has been used 0.8 $\mu\textrm{m}$ BiCMOS device and library of the AMS. IF frequency synthesizer section has been contained IF VCO, Phase Detector, Divide_by_8, Charge Pump and Loop Filter. IF frequency synthesizer has been shown operating voltage of 2.7~3.6 V, control voltage of 0.5~2.7 V and supply current of 11 mA. The measured results have been showed good agreement with the simulation results about supply current.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1935-1940
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• 2016

This paper proposes a phase-locked loop (PLL) to minimize the loop filter output voltage fluctuation by using a comparator including RC time constant circuits. The voltage variation of loop filter is inputted to RC time constant circuits which have two RC time constants, large and small. While a small RC time constant circuit quickly conveys the output voltage variation of loop filter, a large RC time constant circuit conveys slowly the output voltage variation of loop filter and its output looks like constant voltage. The output signal of the comparator controls the sub charge pump and reduces the input voltage variation of voltage-controlled oscillator (VCO). Therefore, the proposed PLL generates a phase noise reduced signal. It has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.2017-2019
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• 2004

본 논문에서는 S/C-밴드(2${\sim}$8GHz)에서 동작하는 초광대역 주파수 합성기를 설계하였다. 먼저 S-밴드(2-4GHz) 광대역 전압제어발진기를 가지고 획득시간을 단축하기 위한 연산 증폭기를 사용한 DA변환기와 능동루프 필터(Active Loop Filter)로 구성된 S-밴드 주파수 합성기를 설계하였다. 그리고 주파수 체배기, SPDT RF 스위치를 통합하여 최종적으로 S/C-밴드 초광대역 주파수 합성기를 설계하였다. 제작된 주파수 합성기는 200kHz 비교주파수에서 위상잡음은 100kHz 옵셋 주파수에서 -92dBc/Hz이하, 불요주파수 특성은 -62.33dBc 이하, 획득시간은 1.3ms 이하로 측정되었다.