• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2731-2740
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• 2012

ASIC(application specific integrated circuit) process is a set of various technologies for fabricating a chip. Generally there have been many researches for RTL design, synthesis, floor plan & routing, low power scheme, clock tree synthesis, and testability which are widely researched in recent. In this paper we propose a new methodology of power strap routing in basis of design experience and experiment. First the power strap for vertical VDD and VSS and horizontal VDD and VSS is routed, and then after the problems which are generated in this process are analyzed, we propose a new process for resolving them. For this, the strap guide is inserted to protect the unnecessary strap routing and dumped for next steps. Next the unnecessary power straps which are generated the first inserting process are removed, and the pre-routing is performed for the macro cells. Finally the resultant power straps are routed using the dumped routing guide. Through the proposed process we identified the efficient and stable route of the power straps.

• KEPCO Journal on Electric Power and Energy
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• v.7 no.1
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• pp.59-62
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• 2021

관형지지물은 단일 강관 기둥 형태의 송전탑으로 강관은 상하 여러 개의 프레임으로 분할되어 플랜지부에서 볼트로 체결된다. 신설 송전선로 관형지지물 플랜지 연결부에서 가압전 조립 볼트 절손이 발견됨에 따라 강관도괴방지 대책 수립을 위한 손상원인분석 기술지원을 수행하였다. 본 건에 대해 파손면·균열 분석 기술을 통해 제작과정 상의 문제가 있었음을 확인하였다.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.1-8
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• 2014

As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.1-10
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• 2011

In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.728-729
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• 2011

Smart Power Grid (SPG) 분야 실증 플랜드 구축과제는 스마트그리드 플랫폼 기반에서 송전, 변전, 배전 분야의 전력기기와 운영 시스템을 통합해 전력망을 효율적, 지능적으로 운전할 수 있는지를 실증하는 프로젝트이다. 현재 스마트그리드 실증단지에는 송전계통의 무효전력관리시스템, 위성망을 이용한 전압위상관리시스템, 송전선로용 볼센서 등을 다루는 지능형 송전, IEC 61850 기반의 IED를 채용한 변전소 자동화, 전기품질 온라인 감시기능을 갖는 지능형 단말장치를 적용 및 변전소 SCADA 기능을 통합 구현하는 배전지능화가 설치되어 있다.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.18_19
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• 2009

서로 다른 이해를 추구하는 다수의 전기사업자가 경쟁하는 전력산업 패러다임의 변화는 전력의 안정적 공급과 이러한 공정한 경쟁이 이루어질 수 있도록 뒷받침 해주는 환경조성이 더욱 절실하게 되었다. 이를 위해 국내는 계통신뢰도및전기품질 유지를 위한 최소 기술적 요건을 정하여 거래소와 전기사업자가 이를 준수하도록 관련 고시가 발효되어있다. 그러나 지난 수년간의 시장체제하에서의 계통신뢰도 확보의 보완사항과 변화하는 대외적 환경변화에 발맞추어 계통신뢰도 기준에 대한 선진화의 필요성이 제기되었으며, 신재생전원 확대, 지능형 송전망 구축 국가적 마스터플랜 등에 따른 기술고시 개정이 논의 중에 있다. 이에 국내 전력계통신뢰도및전기품질 유지 기준 선진화를 위한 제도적, 기술적 현안사항들을 다루어 보고자 한다.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1364-1365
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• 2011

울란바타르시는 몽골의 수도로 인구 110만명이 거주하고 있으며 매년 증가추세에 있다. 2030년에는 몽고 전체인구의 55.5%가 집중되어 도시의 밀집도가 심화될 것으로 예측된다. 몽골은 연평균 강우량이 250mm에도 미치지 못하는 건조한 지역이 대부분으로 전체 수원을 지하수에 의존하고 있으며 인구증가에 따른 지하수 고갈 및 최근 기후변화로 인한 가뭄, 폭설, 한파 등의 영향으로 활용 가능한 수자원이 매년 줄어들고 있어 신규 상수원 확보가 무엇보다 중요시 하고 있다. 동절기 상수원의 결빙을 예방하여야 하나 어려운 전력난으로 전력대신 석탄 보일러를 이용하고 있어 심한 환경오염을 일으키고 있다. 이러한 각종 현상 및 문제점들에 대응코자 진행중인 울란바타르시 수자원개발 마스터플랜 및 상수원 추가 개발사업 가운데 조절지로 공급되는 관로의 잉여압력을 이용한 소수력과 추가되는 가압장의 여유부지에 시설되는 태양광발전의 개발 사례에 대해서 살펴보고자 한다.

• Journal of IKEEE
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• v.16 no.1
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• pp.45-50
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• 2012

This paper proposes the methodology to estimate the routing congestion of modern IC quickly and accurately at the early stage of the design flow. The occurrence of over-congestion in the routing process causes routing failure which then takes unnecessary time to re-design the physical design from the beginning. The precise estimation of routing congestion at the early design stage leads to a successful physical design that minimizes over-congestion which in turn reduces the total design time cost. The proposed estimation method at the block-level floorplan stage measures accurate routing congestion by using the analyzed virtual interconnections of inter/intra blocks, synthesized virtual power/ground and clock networks.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.4
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• pp.220-227
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• 2021

PCT (Power Cable Tunnel) and UT (Utility Tunnel), which are non-transport underground infrastructures, are mostly RC (Reinforced Concrete) structures, and their durability decreases due to the deterioration caused by carbonation over time. In particular, since the rate of carbonation varies by use and region, a predictive model based on actual carbonation data is required for individual maintenance. In this study, a carbonation prediction model was developed for non-transport underground infrastructures, such as PCT and UT. A carbonation prediction model was developed using multiple regression analysis and deep neural network techniques based on the actual data obtained from a safety inspection. The structures, region, measurement location, construction method, measurement member, and concrete strength were selected as independent variables to determine the dependent variable carbonation rate coefficient in multiple regression analysis. The adjusted coefficient of determination (Ra2) of the multiple regression model was found to be 0.67. The coefficient of determination (R2) of the model for predicting the carbonation of non-transport underground infrastructures using a deep neural network was 0.82, which was superior to the comparative prediction model. These results are expected to help determine the optimal timing for repair on carbonation and preventive maintenance methodology for PCT and UT.