• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1310-1311
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• 2011

본 논문에서는 신개념의 에너지 하베스팅 기술로서 전력선의 표유전계에너지 하베스팅을 제안하였고, 저전력 무선 센서노드에 전력공급이 가능함을 실험적으로 확인하였다. 전류가 흐르지 않는 무부하 상태의 220 V 전력선에 20 cm 길이의 알루미늄 포일을 감아서 하베스팅 할 때, 하베스터 회로의 접지가 220 V 전력선의 접지선에 연결되어 있는 경우, 수집 가능한 평균전류는 900 nA, 연구실 콘크리트 바닥에 접지되어 있을 경우, 700 nA의 평균전류를 얻을 수 있음을 확인하였다. 콘크리트 바닥에 접지되어 있는 하베스터 회로의 경우 220 V 전력선으로부터 접지선을 따로 빼 낼 필요가 없기 때문에 충분히 실용적이며 알루미늄 포일의 길이를 60 cm로 느리면 약 2분 만에 저전력 무선 센서노드 구동을 위해 필요한 에너지인 약 2 mJ 만큼 하베스팅이 가능하다. 본 기술을 적용하면 유비쿼터스 센서 네트워크의 전력을 공급할 수 있을 것으로 사료된다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.5
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• pp.938-943
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• 2007

In this paper, we show that, in case of piezoelectric micropower generator, just replacing Schottky diodes in the bridge rectifier with ultra-low reverse leakage current diodes improves the mechanical-to-electrical energy conversion efficiency by more than 100%. Experimental and PSPICE simulation results show that, due to the ultra-low leakage current, the charging speed of the circuit employing PAD1 is higher than that of the circuit employing Schottky diodes and the saturation voltage of the circuit employing PAD1 is also higher. This study suggests that , when the internal impedance of source is very large (a few tens of $M{\Omega}$) such that maximum charging current is a few microamperes or less, in order to realize literally the energy scavenging system, ultra-low reverse leakage current diodes should be used for efficient energy conversion. Since low-level vibration is ubiquitous in the environment ranging from human movement to large infrastructures and the mechanical-to-electrical energy conversion efficiency is much more critical for use of these vibrations, we believe that the improvement in the efficiency using ultra-low leakage diodes, as found in this work, will widen greatly the application of piezoelectric micropower generator.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.1-8
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• 1998

In this paper, we designed a low power 8bit ELM adder with static CMOS and hybrid logic styles on a chip. The designed 8bit ELM adder with both logic styles was fabricated in a 0.8$\mu\textrm{m}$ single-poly double-metal, LG CMOS process and tested. Hybrid logic style consists of CCPL(Combinative Complementary Pass-transistor Logic), Wang's XOR gate and static CMOS for critical path which determines the speed of ELM adder. As a result of chip test, the ELM adder with hybrid logic style is superior to the one with static CMOS by 9.29% in power consumption, 14.9% in delay time and 22.8% in PDP(Power Delay Product) at 5.0V supply voltage, respectively.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.2
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• pp.195-200
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• 2011

A low power Hall thruster is under development for orbit maintenance of a small Earth observing satellite. Both cylindrical and annular type thrusters were manufactured and tested to characterize the performance of cylindrical Hall thrusters. Results were described through comparative analyses. Cylindrical thrusters were manufactured in two different channel diameter dimensions, 28 mm and 50 mm. Thrust, ion velocity and ion current were measured in various operating conditions. The results show that cylindrical thrusters are more efficient in mass utilization and voltage utilization, but less efficient in current utilization than annular one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.227-230
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• 2009

This paper presents an architecture of various devices convergence for ubiquitous network. Integration of a variety of devices be can connect to every kind of device should not be constrained. We construct PLC to UPnP protocol architecture and UPnP Bridge Module for interconnecting Non-IP devices with heterogeneous network interfaces to UPnP devices on UPnP networks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.15-24
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• 2009

This paper proposes an effective low power BIST architecture using the pattern mapping method for 100% fault coverage and the transition freezing method for making high correlative low power patterns. When frozen patterns are applied to a circuit, it begins to find a great number of faults at first. However, patterns have limitations of achieving 100% fault coverage due to random pattern resistant faults. In this paper, those faults are covered by the pattern mapping method using the patterns generated by an ATPG and the useless patterns among frozen patterns. Throughout the scheme, we have reduced an amount of applied patterns and test time compared with the transition freezing method, which leads to low power dissipation.

• Elastomers and Composites
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• v.44 no.4
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• pp.401-407
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• 2009

Commercial grades of solution styrene-butadiene rubbers extended with high aromatic oils having high polycyclic aromatic compounds (PCA) and low PCA oils were used to study the effect of the processing oil particularly on the crack propagation resistance and frictional wear resistance of the vulcanizates. The aromatic oil based vulcanizates exhibited superior fracture behavior over the low PCA oil extended vulcanizates based on tensile and trouser tear tests. Compounds with aromatic oil showed superior crack propagation resistance compared with those containing low PCA oil, especially at the lower ranges of tearing energy. In terms of frictional wear resistance, the aromatic oil extended compounds showed superior performance particularly in the lower frictional work ($W_f$) range but in the higher $W_f$ range the low PCA oil extended vulcanizates performed better.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.29-35
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• 2010

In this paper we propose a new pattern generator for a BIST architecture that can reduce the power consumption during test application. The principle of the proposed method is to reconstruct an LFSR circuit to reduce WSAs of the heavy nodes by suppressing the heavy inputs. We propose algorithms for finding heavy nodes and heavy inputs. Using the Modified LFSR which consists of some AND/OR gates trees and an original LFSR, BIST applies modified test patterns to the circuit under test. The proposed BIST architecture with small hardware overhead effectively reduces the average power consumption during test application while achieving high fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 30.5%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$

• Journal of the Korean Institute of Landscape Architecture
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• v.40 no.3
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• pp.91-98
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• 2012

The objective of this study was to analyze the effects on the growth of Sedum species by different soil in shallow green roof module system, and to find the best soil mixture. The experiment used a module system, 7cm soil depth, five types of soil mixture ratio, and it was carried out on 7th Hoar rooftop in December of 2010. The growth status of the plant showed the most superior of the P5C7P2V1, next P10C1P2V1 and P1P1V1, P1 and C1 showed very poor growth. This result showed that the soil mixture ratio (P5C7P2V1) in green roof module system with minimum management can contribute to the proliferation of rooftop greening in urban settings.