• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.134-139
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• 2006

In this paper we present the Low-Power Bus Driven Floorplan(BDF) in which the bus power consumption is minimized by using a new cost function. The previously reported BDF has used the cost function which minimizes only the chid and the bus area. However, such a cost function may not consider the bus power consumption determined by the topology of a bus in case of the segmented bus design. In this paper, we formulate a new cost function which. reflects the communication frequency and the real distance between blocks in a bus to model the bus power consumption. For the Low-Power BDF with the new cost function, the experimental results show the bus power consumption cost is reduced by 11.43% on the average.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.437-444
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• 2010

The audio data have been communicated using analog methods or simple protocols. However, with the advent and improvement of various multimedia functions, many audio devices have been integrated into a mobile handset in which interconnection lines are very complicated. Conventional point-to-point connections such as $I^2S$ and PCM demand more power consumption whenever more devices are attached. In this paper, we design a common bus digital audio interface that communicates with only two wires and employs the clock gear method to reduce bus power consumption. The comparison results show that the proposed common bus connection can reduce more than 30% of power consumption as compared with point-to-point connection if more than three devices are connected.

• The Journal of the Korea Contents Association
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• v.7 no.11
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• pp.84-93
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• 2007

This paper presents a methodology that accelerates estimating the system-level power consumption for on-chip bus of SoC platforms. The proposed power modeling can estimate the power consumption according to the change of a target SoC system. The proposed model comprises two parts: the one is power estimation of bus logics reflecting the architecture of the bus such as the number of bus layers, the other is to estimate the power consumed by the bus lines during data transmission. We designed the target multimedia SoC system, MPEG encoder as an example and evaluated power consumption using this model. The simulation result shows that the accuracy of the proposed model is over 92%. Thus, the proposed power model can be used to design of a high-performance/low-power multimedia SoC.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.12
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• pp.680-686
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• 2002

In deep-submicron (BSM) design, coupling effects between wires on the bus cause serious problems such as crosstalk delay, noise, and power consumption. Most of the previous works on bus encoding are targeted either to minimize tile power consumption on bus or to minimize the crosstalk delay, but not both. In this paper, we propose a new bus encoding algorithm that minimizes the power consumption on bus and eliminates the crosstalk delay simultaneously. We formulate and solve the problem by minimizing a weighted sum of the self transition and cross-coupled transition activities on bus From experiments using a set of benchmark designs. it is shown that the proposed encoding technique consumes at least 15% less power over the existing techniques, while completely eliminating the crosstalk delay.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06d
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• pp.24-27
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• 2011

최근 스마트 폰 등 모바일 기기의 폭발적인 성장에 의해 내장 프로세서인 ARM 프로세서 기반 기기들이 활발히 개발되어 사용되고 있다. 이에 따라 상대적으로 저성능, 저 전력화에 치중하였던 내장 프로세서도 고성능화를 위한 고속 동작 및 멀티코어 프로세서를 개발하여 사용하게 되었으며, 메모리 동작 속도 역시 빠르게 발전하고 있다. 특히 모바일 기기 등에 사용 되는 저전력 메모리인 LPDDR2 소자 등의 개발에 따라 빠른 동작 속도를 가지도록 개발되고 있다. 그러나 시스템 온 칩(SoC, System on Chip) 형태로 제작되는 ARM 프로세서 기반의 SoC는 다양한 하드웨어 가속기 등을 함께 내장하고 있고, 저 전력화를 위한 버스 구조 등에 의하여 온 칩 버스의 속도 향상이 고성능 범용 시스템에 비하여 낮은 수준이다. 본 연구에서는 이러한 점을 고려하여, 프로세서 코어와 메모리 소자의 동작 속도 향상에 의하여 얻을 수 있는 성능 향상과, 상대적으로 낮은 버스 동작 속도에 의하여 저하되는 성능의 정도를 분석하고 이를 극복하기 위한 방안을 검토하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.553-555
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• 2004

SoC 분야에서 온 칩 버스는 전체 시스템의 성능을 결정하는 중요한 요소이다. 이에 따라 최근 ARM 사에서는 고성능 온 칩 버스 구조인 ML(Multi-Layer) AHB 버스를 제안하였다. ML AHB 버스는 저전력 임베디드 시스템에 적합한 버스 구조로써 현재 널리 사용되고 있다. 하지만, 고가이기 때문에 ADK(AMBA$^{TM}$ Design kit) 구매에 대한 부담이 적지 않다. 본 논문은 ML AHB의 버스 구조인 버스 매트릭스 구현 및 ADK에서 제공되지 않는 테스트 환경 즉, Protocol Checker 및 Performance Monitor Module 구현에 관한 것이다.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.27-29
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• 2000

버스-인버트 코딩 기법은 버스에서의 연속된 데이터 전송시 발생하는 데이터 값의 천이를 줄이는 기법이다. 기존의 방식에서는 전체버스 라인이나 그중의 한 일부분만에 버스-인터트 코딩을 적용했었던 것과는 달리, 우리의 기법은 버스 라인들을 몇 개의 묶음으로 분할하여, 각 묶음에 대해 독립적으로 버스-인버트 코딩을 적용하여 데이터 값의 천이를 최소화 하려고 한다. 실험을 통해서 우리의 기법은 데이터 값의 천이를 전체적으로 10-50% 감소시킬수 있음을 나타났다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.11
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• pp.1577-1585
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• 2022

As the interest in the 4th industrial revolution and metaverse increases, metaverse with multi edge structure is proposed and noted. Metaverse is a structure that can create digital doctor-like system through a large amount of image processing and data transmission in a multi edge system. Since metaverse application requires calculating performance, which can reconstruct 3-D space, edge hardware's insufficient calculating performance has been a problem. To provide streamable AI software in runtime, image processing, and data transmission, which is edge's loads, needs to be lightweight. Also lightweight at the edge leads to power consumption reduction of the entire metaverse application system. In this paper, we propose collaborative edge-cloud image processing with remote image processing method and Region of Interest (ROI) to overcome edge's power performance and build streamable and runtime executable AI software. The proposed structure was implemented using a PC and an embedded board, and the reduction of time, power, and network communications were verified.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.71-79
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• 2004

Packet-type data transmission is characterized by the continuous transmission of massive data with relatively constant rate. In such transmission, the dynamic power consumed on buses is influenced by the sequence of transmitted data. A new coding scheme called Sequence-Switch Coding (SSC) is proposed in this paper. SSC reduces the number of bus transitions in the transmission of packet-type data by changing the sending order of the data. Some simple algorithms are presented, In. The simulation results show that SSC outperforms the well-known Bus-Invert Coding with these algorithms. SSC is not a specific algerian but a method to reduce the number of bus-transitions. There could be lots of algorithms for realizing SSC. The variety of SSC algorithms provides circuit designers a wide range of trade-off between performance and circuit complexity.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.223-224
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• 2016

본 논문은 상용급 전기버스의 24 V 전장전력공급장치로써 고전압배터리부터 저전압으로 변성하는 전력변환장치인 저전압 직류변환장치 (Low Voltage DC/DC Converter : LDC) 개발에 관하여 기술한다. 제안하는 LDC는 효율을 높이기 위해 트랜스포머 1차 측 위상천이 전브리지 스위칭 소자에 SiC MOSFET을 사용하고, 2차 측에 동기정류방식을 적용하였다. 고효율 성능을 검증하기 위해 시작품을 제작하고 시험을 통해 3 kW 97% 이상의 고효율, 고출력, 고밀도의 특성을 확인하였다.