• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.4
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• pp.387-396
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• 2013

This paper investigates the droop control of parallel inverters for an islanded mode of microgrid. Frequency and voltage droop control is one of power control and load demand sharing methods. However, although the active power is properly shared, the reactive power sharing is inaccurate with conventional method due to the unequal line impedances and the power coupling of active - reactive power. In order to solve this problem, an improved droop method with virtual inductor concept and a voltage and current controller properly designed have been considered and analyzed through the PSiM simulation. The performance of improved droop method is analyzed in not only low-voltage line but also medium voltage line.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.04a
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• pp.1179-1182
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• 2017

최근 사물인터넷(IoT, Internet of Things)관련 기술의 발전 및 서비스 산업의 급속한 발전으로 센서 장치에 대한 수요가 증가하고 있다. 센서 장치는 사물인터넷 플랫폼과의 연동을 위한 통신 인터페이스를 필수로 지원하여야 하며, 그 외에 다양한 센서들의 연동 인터페이스와 소비 전력을 모두 고려하여 하드웨어 및 소프트웨어의 설계가 이루어져야 한다. 이와 같이 센서 장치는 베터리 소비를 최적화하여 모든 기능이 구현되어야 하므로 기능상의 제약이 많이 따른다. 시간 동기화를 위해 사물인터넷 플랫폼에서 송신하는 동기 메시지를 수신하기 위해 슬립모드를 지원하는 경우 센서 장치가 항상 깨어 있어 야하므로 저전력으로 동작 할 수 없는 어려움이 따른다. 따라서 사물인터넷망에서 시간동기화를 위한 마스터 클럭을 선정 방법을 제안하고 이를 위한 단일 프레임 방식을 제안한다. 향후 시간 동기화 프로토콜의 호환을 위해 CoAP 규격과 연동 될 수 있는 연구가 필요하다.

• Journal of Broadcast Engineering
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• v.19 no.4
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• pp.491-501
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• 2014

Recently, the need for disaster-preventing broadcast has increased gradually to cope with natural disaster like earthquake and tsunami causing enormous losses of both life and property. In disaster-preventing broadcast system, the wake-up signal is used to alert user terminal and switch the current state of channel to the emergency channel, which is for the fast and efficient delivery of emergency information. In this paper, we propose the detection method of wake-up signal for disaster-preventing broadcast systems. The wake-up signals for disaster-preventing broadcast should have a good auto-correlation property in low power and narrow-band conditions that does not affect the existing digital television (DTV) system. The suitability of the m-sequence and complementary code (CC) is analyzed for wake-up signals according to signal to noise ratio. A wake-up signal is proposed by combining the direct sequence spread spectrum (DSSS) technique and pseudo noise (PN) sequences such as Barker and Walsh-Hadamard codes. By using the proposed method, a higher detecting performance can be achieved by the spreading gain compared to the single long m-sequence and the Golay code.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.40-48
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• 2013

This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.1-7
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• 2008

This paper proposes 3.3V input and 1.8V output voltage mode step-down DC-DC buck converter for wireless mobile system which is designed in a standard 0.35$\mu$m CMOS process. The proposed capacitor multiplier method can minimize error amplifier compensation block size by 30%. It allows the compensation block of DC-DC converter be easily integrated on a chip. Also, we improve efficiency to 3% using low power buffer. Measurement result shows that the circuit has less than 1.17% output ripple voltage and maximum 83.9% power efficiency.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.5
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• pp.1-13
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• 2009

Filter cache has been introduced as one solution of reducing cache power consumption. More than 50% of the power reduction results from the filter cache, whereas more than 20% of the performance is compromised. To minimize the performance degradation of the filter cache, the predictive filter cache has been proposed. In this paper, we review the previous filter cache predictors and analyze the problems of the solutions. As a result, we found main problems that cause prediction misses in previous filter cache schemes and, to resolve the problems, this paper proposes a new prediction policy. In our scheme, some reference bit entries, called MSBs, are inserted into filter cache and BTB, to adaptively control the filter cache access. In simulation parts, we use a modified SimpleScalar simulator with MiBench benchmark programs to verify the proposed filter cache. The simulation result shows in average 5% performance improvement, compared to previous ones.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1792-1798
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• 2010

Home Gateway is always on for continuous services of home networks. Ubiquitous home networks are extended. so power consumption of home gateways increases by geometric progression. Our algorithm is for home gateway to sleep, listen or wakeup according to network traffic adaptively, as well as to keep always-on service. To do this, it traces the accumulated average of previous sleep periods. In addition to this basic algorithm, we make the profiles for user's living pattern per the day to reflect network usages in detail and adaptively. As the simulation results by comparing with overall accumulated average and per-day accumulated average, in case of the overall accumulated average, the difference the estimation and real value is distributed from 0.43% to 4%. In contrast of this, in case of the per-day accumulated average is distributed from 0.06% to 2%. From this results, we know the profiling of per-day usage pattern can help reduce the difference of the real sleep period and the estimated sleep period.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.135-144
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• 2003

This work proposes on-chip full CMOS current and voltage references for high-speed mixed-mode circuits. The proposed current reference circuit uses a digital-domain calibration method instead of a conventional analog calibration to obtain accurate current values. The proposed voltage reference employs internal reference voltage drivers to minimize the high-frequency noise from the output stages of high-speed mixed-mode circuits. The reference voltage drivers adopt low power op amps and small- sized on-chip capacitors for low power consumption and small chip area. The proposed references are designed, laid out, and fabricated in a 0.18 um n-well CMOS process and the active chip area is 250 um x 200 um. The measured results show the reference circuits have the power supply variation of 2.59 %/V and the temperature coefficient of 48 ppm/$^{\circ}C$ E.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.517-531
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• 1999

This paper presents the development of the 2-mode variable gain high power amplifier for a transmitter of INMARSAT-M operating at L-band(1626.5-1646.5 MHz). This SSPA(Solid State Power Amplifier) is amplified 42 dBm in high power mode and 36 dBm in low power mode for INMARSAT-M. The allowable error sets +1 dBm of an upper limit and -2 dBm of a lower limit, respectively. To simplify the fabrication process, the whole system is designed by two parts composed of a driving amplifier and a high power amplifier, The HP's MGA-64135 and Motorola's MRF-6401 are used for driving amplifier, and the ERICSSON's PTE-10114 and PTF-10021 are used the high power amplifier. The SSPA was fabricated by the circuits of RF, temperature compensation and 2-mode gain control circuit in aluminum housing. The gain control method was proposed by controlling the voltage for the 2-mode. In addition, It has been experimentally verified that the gain is controlled for single tone signal as well as two tone signals. The realized SSPA has 42 dB and 36 dB for small signal gain within 20 MHz bandwidth, and the VSWR of input and output port is less than 1.5:1 The minimum value of the 1 dB compression point gets 5 dBm for 2-mode variable gain high power amplifier. A typical two tone intermodulation point has 32.5 dBc maximum which is single carrier backed off 3 dB from 1 dB compression point. The maximum output power of 43 dBm was achieved at the 1636.5 MHz. These results reveal a high power of 20 Watt, which was the design target.the design target.