• Journal of KIISE:Computing Practices and Letters
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• v.16 no.4
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• pp.462-466
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• 2010

A new buffer cache management scheme that aims at reducing power consumption in mixed HDD and NAND flash memory storage systems is presented. The proposed scheme reduces power consumption by considering different energy-consumption rate of storage devices, I/O operation type (read or write), and reference potential of cached blocks in terms of both recency and frequency. Simulation shows that the proposed scheme reduces power consumption by 18.0% on average and up to 58.9%.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.290-292
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• 2012

클라우드 컴퓨팅에서는 사용량 당 과금 정책을 통해 서비스를 제공하여 사용자에게 높은 수준의 QoS 를 제공함과 동시에 비용절감의 효과를 가지고 있다. 하지만 클라우스 서비스 제공 업체에서는 최대 서비스 요구량을 만족시킬 수 있도록 시스템을 구성해야 할 필요가 있으며, 이에 맞추어 상당한 시간동안 다수의 자원을 유휴상태로 운영하여야 한다. 데이터 센터를 유휴상태로 운영될 경우 즉시 서비스 제공이 가능하다는 장점이 있으나 반대로 전력을 낭비한다는 단점을 가진다. 본 연구는 최소한의 전력소모를 하면서 QoS 를 보장할 수 있도록 하는 시스템 구축 모델을 제시하는 데 목적이 있으며 시뮬레이션 결과를 통하여 우리가 제시한 모델의 적절성을 보이려고 한다. 우리의 모델은 요청 작업 타입에 따른 traffic shaping 기법을 도입하여 작업을 저전력 컴퓨터와 고성능 컴퓨터에 분산배치하도록 하는데 목적이 있으며 가상화 기법을 통해 작업의 신속한 분산작업을 수행하는 방법을 사용한다.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.2
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• pp.143-150
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• 2003

An improved MPPT converter with current compensation method for small-scaled PV-applications is presented in this paper. The proposed method implements maximum power point tracking (MPPT) by variable reference current which is continuously changed during one sampling period. Therefore, the Power transferred to the load is increased above 9% by the proposed MPPT converter with current compensation method. As a result, the utilization efficiency of Photovoltaic (PV)-panel can be increased. In addition, as it doesn't use digital signal processor (DSP), this MPPT method has the merits of both a cost efficiency and a simple control circuit design. Therefore, it is considered that the proposed MPPT method is proper to low power, low cost PV-applications. The concept and control principles of the proposed Un moth()d are explained in detail and its validity of the proposed method is verified through several simulated results.

• Journal of the Korea Society of Computer and Information
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• v.13 no.6
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• pp.33-39
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• 2008

Energy efficiency should be considered together with performance when designing embedded processors. This paper proposes a new energy-aware instruction cache design using backward branch information to reduce the energy consumption in an embedded processor, since instruction caches consume a significant fraction of the on-chip energy. Proposed instruction cache is composed of two caches: a large main instruction cache and a small loop instruction cache. Proposed technique enables the selective access between the main instruction cache and the loop instruction cache to reduce the number of accesses to the main instruction cache, leading to good energy efficiency. Analysis results show that the proposed instruction cache reduces the energy consumption by 20% on the average, compared to the traditional instruction cache.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.1
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• pp.26-33
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• 2013

Femto-cells are low power/cost, micro-base stations and are main components in heterogeneous networks. However, some of technical issues arise when femto-cells are initially installed. One approach to resolve the problems is to control the transmission (TX) power autonomously via SON(Self-Organized Network) scheme. By controlling the femto-cell TX power, the system throughput performance can be improved or the system overhead is highly reduced. Generally, the TX power for maximizing the system throughput and that for reduced system overhead may not be identical. Therefore, we propose a TX power control scheme by which we can improve the system throughput and reduce the system overhead, simultaneously. When we apply the proposed method, the simulation results show that the system overhead can be reduced by up to 41% compared to the performance of the method which maximizes throughput performance only, and the throughput performance can be improved by up to 63% compared to that of the method which only optimizes the coverage area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.76-83
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• 2007

This paper describes a low power ROM using single charge-sharing capacitor and hierarchical bit line (SCSC-ROM). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a very small voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and make easy to design. The hierarchical bit line further saves the power by reducing the capacitance in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with $4K{\times}32bits$consumes only 37% power of a conventional ROM. A SCSC-ROM chip is fabricated in a $0.25{\mu}m$ CMOS process. It consumes 8.2mW at 240MHz with 2.5V.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.574-576
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• 2004

임베디드 시스템에서 입출력에서 소모되는 전력양은 상당한 수준이다. 입출력 장치에서의 수행되는 타스크의 순서를 정하여 전체적으로 입출력 장지에서의 휴식 시간을 최대한 많이 허락하는 기법이 필요하다. 기존의 연구는 입출력 장치 소비 전력 최소화를 위한 타스크 스케줄링 문제를 단순한 지협적인 휴리스틱에 기반하여 풀었다. 본 연구는 기존의 연구에서의 방법과는 달리 최적의 해를 내는 해법을 제시한다. 구체적으로 시간 제약 조건을 가진 저전력을 위한 타스크 스케줄링 문제를 ILP (integer linear programming) 기법을 적용하는 방법을 제시한다. 본 연구는 또한, 실험을 통해 주어진 시간 안에 최적의 해를 구하는 문제의 크기를 판단하는 기준을 제시할 수 있다는 의의를 가진다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.104-110
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• 2006

The huge test data volume, test time and power consumption are major problems in system-on-a-chip testing. To tackle those problems, we propose a new test data compression technique. Initially, don't-cares in a pre-computed test cube set are assigned to reduce the test power consumption, and then, the fully specified low-power test data is transformed to improve compression efficiency by neighboring bit-wise exclusive-or (NB-XOR) scheme. Finally, the transformed test set is compressed to reduce both the test equipment storage requirements and test application time.

• The KIPS Transactions:PartA
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• v.13A no.3 s.100
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• pp.191-198
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• 2006

Today's portable electric consumer devices, which are operated by battery, tend to integrate more multimedia processing capabilities. In the multimedia processing devices, multimedia system-on-chips can handle specific algorithms which need intensive processing capabilities and significant power consumption. As a result, the power-efficiency of multimedia processing devices becomes important increasingly. In this paper, we propose a reconfigurable data caching architecture, in which data allocation is constrained by software support, and evaluate its performance and power efficiency. Comparing with conventional cache architectures, power consumption can be reduced significantly, while miss rate of the proposed architecture is very similar to that of the conventional caches. The reduction of power consumption for the reconfigurable data cache architecture shows 33.2%, 53.3%, and 70.4%, when compared with direct-mapped, 2-way, and 4-way caches respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.757-759
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• 2005

배터리의 용량이 제한적인 핸드헬드 시스템에서의 전력소비를 절감시키기 위한 동적전압변경 기법에 관련한 많은 연구가 이루어지고 있으나, 프로세서나 LCD 같은 각각의 요소에 기반을 둔 저 전력 정책들은 전력절감에 있어 한계에 다다르고 있다. 이를 극복하기 위하여, 본 연구에서는 전력관리의 대표적인 기법인 프로세서 DVS와 LCD 재생 프레임 빈도 제어를 통합한 다차원 전력관리를 시스템 전력관리 차원에서 제시한다. 실제 시스템에서의 구현 결과를 제시함으로써 다차원 동적전압변경 기법이 멀티미디어 응용에 있어서 단일 요소의 전력관리보다 시스템 차원에서의 부가적 전력 절감을 할 수 있음을 보인다.