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http://dx.doi.org/10.3745/KIPSTA.2006.13A.3.191

Low-Power Data Cache Architecture and Microarchitecture-level Management Policy for Multimedia Application  

Yang Hoon-Mo (연세대학교 공과대학 컴퓨터과학과)
Kim Cheong-Gil (연세대학교 공과대학 컴퓨터과학과)
Park Gi-Ho (삼성전자 SOC 연구소 Processor Architecture Lab.)
Kim Shin-Dug (연세대학교 공과대학 컴퓨터과학과)
Publication Information
The KIPS Transactions:PartA / v.13A, no.3, 2006 , pp. 191-198 More about this Journal
Abstract
Today's portable electric consumer devices, which are operated by battery, tend to integrate more multimedia processing capabilities. In the multimedia processing devices, multimedia system-on-chips can handle specific algorithms which need intensive processing capabilities and significant power consumption. As a result, the power-efficiency of multimedia processing devices becomes important increasingly. In this paper, we propose a reconfigurable data caching architecture, in which data allocation is constrained by software support, and evaluate its performance and power efficiency. Comparing with conventional cache architectures, power consumption can be reduced significantly, while miss rate of the proposed architecture is very similar to that of the conventional caches. The reduction of power consumption for the reconfigurable data cache architecture shows 33.2%, 53.3%, and 70.4%, when compared with direct-mapped, 2-way, and 4-way caches respectively.
Keywords
Low-power; Microarchitecture; Memory System; Data Cache; Cache Partitioning; Multimedia Application;
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  • Reference
1 Premkishore Shivakumar, Norman P. Jouppi, 'CACTI 3.0: An Integrated Cache Timing, Power, and Area Model,' WRL Research Report, 2001
2 Hsien-Hsin S. Lee, Gary S. Tyson, 'Region-Based Caching: An Energy-Delay Efficient Memory Architecture for Embedded Processors,' Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp.120-127, 2000   DOI
3 MiBench Version 1.0, http//www.eecs.umich.edu/mibench
4 Matthew R. Guthaus, Jeffrey S. Ringenberg, Dan Ernst, Todd M. Austin, Trevor Mudge, Richard B. Brown, 'MiBench: A free, commercially representative embedded benchmark suite,' IEEE 4th Annual Workshop on Workload Characterization, 2001
5 MPEG Software Simulation Group, http://www.mpeg.orgIMPEG/MSSG
6 SimpleScalar LLC, http://www.simplescalar.com
7 Western Research Laboratory, http://research.compaq.com/wrl/people/jouppi/CACTI.html
8 Jayaprakash Pisharath, Alok N. Choudhary, 'An Integrated Approach to Reducing Power Dissipation in Memory Hierarchies,' Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp.88-97, 2002   DOI
9 Nathaniel Pettis, Le Cai, and Yung-Hsiang Lu, 'Dynamic Power Management for Streaming Data,' Proceedings of the International Symposium on Low Power Electronics and Design, pp.62-65, 2004   DOI
10 Daniel F. Zucker, Ruby B. Lee, Michael J. Flynn, 'Hardware and Software Cache Prefetching Techniques for MPEG Benchmarks,' IEEE Transactions of Circuits and Systems for Video Technilogy, Vol.10, No.5, pp782-796, 2000   DOI   ScienceOn
11 Valentin Muresan, Noel O'Connor, Noel Murphy, Sean Marlow, Stephen McGrath, 'Low Power Techniques for Video Compression,' Irish Signals and Systems Conference, Cork, Ireland, 2002
12 Peter Soderquist, Miriam Leeser, 'Optimizing the Data Cache Performance of a Software MPEG-2 Video Decoder,' Proceedings of the 5th ACM International Conference on Multimedia, pp.291-30l, 1997   DOI
13 Sohum Sohoni, Zhiyong Xu, Rui Min and Yiming Hu, 'A Study of Memory System Performance of Multimedia Applications,' Proceedings of the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, pp.206-215, 2001   DOI