• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.58-60
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• 2001

제한된 전력 원을 사용하는 휴대용기기의 대중화에 따라 제한된 전력 원을 보다 효율적으로 사용할 수 있게 하는 저 전력에 대한 연구가 활발히 진행 중에 있다. 특히 휴대용 기기의 성능이 더욱더 고성능화 됨에 따라 휴대용 기기에도 SRAM, DRAM, SDRAM등의 각종 메모리 시스템이 사용되기 시작하였다. 또한 이러한 메모리 시스템은 전체 시스템에 있어서 주요한 전력소모 요인이 되었다 따라서 본 논문에서는 이러한 메모리 장치에 대한 전력 소모 특성을 분석 수행하였으며 분석 수행 방법에 있어서 기존의 방법과는 다르게 Address, Data, 제어신호등에 따른 에너지 소모 특성을 분석함으로서 기존의 연구와는 다르게 H/W차원뿐 아니라 더 상위레벨의 S/W차원가지의 에너지 소모 절감 기법 개발을 위한 흑은 저 전력 S/W 제작을 위한 자료로서 사용될 수 있는 기초 자료를 제공하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.509-514
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• 2008

동적 전력 관리 기법은 임베디드 시스템과 같은 저전력성이 요구되는 시스템에서 널리 활용되고 있다. 동적 전력 관리 기법은 처리율과 소비전력 간의 상관 관계를 통해, 프로세서의 전압과 주기를 조절하여 소비 전력당 처리율을 높이는 기법이다. 이러한 동적 전압 관리 기법이 실시간 특성이 필요한 임베디드 시스템에 적용되는 경우, 실시간 스케줄러에 큰 영향을 끼치게 된다. 실시간 스케줄러에서는 주어진 임계 시간 이내에 작업의 수행을 마치기 위하여, 스케줄 가능성 테스트를 수행하여 적합한 작업들만을 실행하도록 한다. 하지만, 인터럽트 처리 등으로 인한 선점 가능성은 스케줄 가능성에 대한 분석을 복잡하게 만들고 있다. 본 논문에서는 인터럽트 처리를 고려한 실시간 스케줄링 분석 연구를 기반으로 하여, 동적 전력 관리가 추가된 경우의 영향을 분석하도록 한다. 동적 전력 관리로 인한 실시간 처리 요구 사항의 증가와 실제 적용 가능한 사례를 보인다.

• Journal of Korea Multimedia Society
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• v.11 no.5
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• pp.641-650
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• 2008

As portable devices are used widely, power management algorithm is essential to extend battery use time on small-sized battery power. Although many methods have been proposed, they assumed the voltage transition overhead was negligible or was considered partially. However, the voltage transition overhead might not guarantee to schedule real-time tasks in portable multimedia systems. This paper proposes the adaptive power-aware algorithm to minimize the power consumption by considering the voltage transition overhead. It selects only a few discrete frequencies from the whole frequencies of a system and adjusts the interval between two consecutive frequencies based on the system utilization to reduce the number of frequency change. This algorithm saves the power consumption about 10 to 25 percent compared to a CC RT-DVS method and a frequency-smoothing method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.503-509
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• 2007

Low-power motion estimation is required for video coding in portable information devices. In this paper, we propose a low-power motion estimation algorithm and 1-D systolic may VLSI architecture using full search block matching algorithm (FSBMA). Main power dissipation sources of FSBMA are complex computations and frequent memory accesses for data in the search area. In the proposed algorithm, memory accesses and computations are reduced by using 1D PE (processing array) array architecture performing motion estimation of two neighboring blocks in parallel and by skipping unnecessary computations during motion estimation. The VLSI implementation results of the algorithm show that the proposed VLSI architecture can save 9.3% power dissipation and can operate two times faster than an existing low-power motion estimator.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.197-200
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• 2011

Many routing protocols have been proposed for low-power and ad-hoc networks where energy awareness and reliability are essential design issues. This paper proposes a dynamic routing protocol for low-power and ad-hoc networks. A dynamic path cost function is defined considering the constraints and characteristics of low-power and ad-hoc networks. The cost function can be applied flexibly depending on the characteristics of the networks. The performance of the proposed method is evaluated using a QualNet network simulator.

• Journal of the Korea Society of Computer and Information
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• v.14 no.12
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• pp.9-16
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• 2009

Energy consumption as well as performance should be considered when designing up-to-date multicore processors. In this paper, we propose new design technique to reduce the energy consumption in the instruction cache for multicore processors by using modified filter cache. The filter cache has been recognized as one of the most energy-efficient design techniques for singlecore processors. The energy consumed in the instruction cache accounts for a significant portion of total processor energy consumption. Therefore, energy-aware instruction cache design techniques are essential to reduce the energy consumption in a multicore processor. The proposed technique reduces the energy consumption in the instruction cache for multicore processors by reducing the number of accesses to the level-1 instruction cache. We evaluate the proposed design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed architecture reduces the energy consumption in the instruction cache for multicore processors by up to 3.4% compared to the conventional filter cache architecture. Moreover, the proposed architecture shows better performance over the conventional filter cache architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.134-139
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• 2006

In this paper we present the Low-Power Bus Driven Floorplan(BDF) in which the bus power consumption is minimized by using a new cost function. The previously reported BDF has used the cost function which minimizes only the chid and the bus area. However, such a cost function may not consider the bus power consumption determined by the topology of a bus in case of the segmented bus design. In this paper, we formulate a new cost function which. reflects the communication frequency and the real distance between blocks in a bus to model the bus power consumption. For the Low-Power BDF with the new cost function, the experimental results show the bus power consumption cost is reduced by 11.43% on the average.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.5
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• pp.193-197
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• 2017

In this paper, we present a low-power delta-sigma based digital frequency synthesizer with high frequency resolution for bio sensor networks. Biomedical radio-frequency (RF) transceivers require miniaturized forms with a long battery life and low power consumption. For the technology scaling, digital circuits have become preferable compared to analog circuits because of the aggressive cost, size, flexibility, and repeatability. Therefore, the digital circuits based on standard-cell library are used to reduce a power consumption. Additionally, a delta-sigma is used for making fractional frequency tuning range. From the simulation, we confirmed that proposed scheme has good performance in accordance with power and frequency resolution.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.17-29
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• 1999

This paper presents a high level synthesis method targeting low power consumption for data-dominated CMOS circuits (e.g., DSP). The high level synthesis is divided into three basic tasks: scheduling, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph, a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network to obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces both the switching activity and the capacitance in synthesized data path. Experimental results show 15% power reduction in benchmark circuits.