• Journal of IKEEE
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• v.28 no.1
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• pp.78-89
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• 2024

PMIC chips based on a BCD process used in automotive semiconductors require multi-time programmable (MTP) intellectual property (IP) that does not require additional masks to trim analog circuits. In this paper, MTP cell size was reduced by about 18.4% by using MTP cells using PMOS capacitors (PCAPs) instead of NMOS capacitors (NCAPs) in MTP cells, which are single poly EEPROM cells with two transistors and one MOS capacitor for small-area MTP IP design. In addition, from the perspective of MTP IP circuit design, the two-stage voltage shifter circuit is applied to the CG drive circuit and TG drive circuit of MTP IP design, and in order to reduce the area of the DC-DC converter circuit, the VPP (=7.75V), VNN (=-7.75V) and VNNL (=-2.5V) charge pump circuits using the charge pumping method are placed separately for each charge pump.

• Review of KIISC
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• v.29 no.5
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• pp.31-36
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• 2019

초고속, 초저지연, 초연결 특성으로 대표되는 5G 시대가 도래함에 따라 새로운 통신 환경과 서비스 환경에 적합한 암호기술이 요구되고 있다. IoT 환경 등 자원이 제약된 기기를 위한 저면적/저전력 암호기술, 자율 주행 등 실시간 처리를 위한 저지연 암호기술 등 경량암호에 대한 요구사항 또한 다변화되고 있다. 본 고에서는 SPECK/SIMON, LEA 등으로 대표되는 경량 블록암호와 초저지연 암호기술에 대해 살펴보고 NIST에서 진행 중인 경량암호 공모사업을 소개한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.96-103
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• 2008

This paper proposes a new low-power and small-area Reed-Solomon decoder. The proposed Reed-Solomon decoder using a novel simplified form of the modified Euclid's algorithm can support low-hardware complexity and low-Power consumption for Reed-Solomon decoding. The simplified modified Euclid's algorithm uses new initial conditions and polynomial computations to reduce hardware complexity, and thus, the implemented architecture consisting of 3r basic cells has the lowest hardware complexity compared with existing modified Euclid's and Berlekamp-Massey architectures. The Reed-Solomon decoder has been synthesized using the $0.18{\mu}m$ Samsung standard cell library and operates at 370MHz and its data rate supports up to 2.9Gbps. For the (255, 239, 8) RS code, the gate counts of the simplified modified Euclid's architecture and the whole decoder excluding FIFO memory are only 20,166 and 40,136, respectively. Therefore, the proposed decoder can reduce the total gate count at least 5% compared with the conventional DCME decoder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.47-55
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• 2010

In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.

• Journal of Oral Medicine and Pain
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• v.17 no.2
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• pp.109-117
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• 1992

저출력레이저는 인체조직에 biostimulation effects를 가지므로 구강주위에 발생하는 여려가지 질병에 대한 저출력레이저광의 효과에 관하여 많은 연구가 시도되고 있으며 또한 치료에 응용되고 있다. 감염창상에 저출력레이저 조사시 조직치유의 기전이 세균 성장에 의한 조직손상보다 주위 정상조직의 biostimulation effects가 우세하기 때문이라는 가설을 확인하고저 본 연구를 시행하였다. 백서 7마리를 레이저 조사군과 대조군으로 나누어 감염창상의 면적차이를 비교하여 다음고 같은 결론을 얻었다. 1. 저출력레이저 조사군에서 창상수축율이 현저히 높았다. 2. 부종의 빈도는 저출력레이저 조사시 뚜렷하게 감소하였다. 위의 사실로 보아 저출력레이저 조사시 감염창상의 치유촉진은 주위 정상조직의 biostimulation effect가 세균증식에 의한 조직의 손상보다 우세하기 때문이라는 가설을 확인할 수 있었다.

• Journal of radiological science and technology
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• v.40 no.3
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• pp.393-400
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• 2017

The purpose of this study is to suggest a method to reduce the dose by Analyzing the dose area product (DAP) and image quality according to the change of tube current using NEMA Phantom. The spatial resolution and low contrast resolution were used as evaluation criteria in addition to signal to noise ratio (SNR) and contrast to noise ratio (CNR), which are important image quality parameters of intervention. Tube voltage was fixed at 80 kVp and the amount of tube current was changed to 20, 30, 40, and 50 mAs, and the dose area product and image quality were compared and analyzed. As a result, the dose area product increased from $1066mGycm^2$ to $6160mGycm^2$ to 6 times as the condition increased, while the spatial resolution and low contrast resolution were higher than 20 mAs and 30 mAs, Spatial resolution and low contrast resolution were observed below the evaluation criteria. In addition, the SNR and CNR increased up to 30 mAs, slightly increased at 40 mAs, but not significantly different from the previous one, and decreased at 50 mAs. As a result, the exposure dose significantly increased due to overexposure of the test conditions and the image quality deteriorated in all areas of spatial resolution, low contrast resolution, SNR and CNR.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.364-366
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• 2009

광 바이오 센서 시스템에서 Trans-Impedance amplifier (TIA)는 광검출기로부터 입력단으로 들어오는 미세한 전기 신호를 원하는 신호레벨까지 증폭하는 역할을 한다. TIA는 광 바이오 센서 시스템의 감도 (sensitivity)를 결정하는 매우 중요한 회로로 저잡음, 저전력, 낮은 입력 임피던스 등의 특성이 요구되어진다. 본 논문에서는 광 바이오 센서 시스템에서 요구되어 지는 저전력, 저잡음 성능을 구현하기 위하여 regulated cascode (RGC) TIA를 설계하였다. 본 연구에서는 기존 common gate (CG) 기법의 TIA에서 전류원 역할을 하는 current source를 저항으로 대체하고, local feedback stage를 이용하는 RGC TIA를 저잡음, 저전력 특성 및 회로 면적 감소의 장점을 갖도록 설계하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.53-60
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• 2009

A low-power/small-area 128-point FFT processor is designed, which is based on logarithmic number system (LNS) and some design techniques to minimize both hardware complexity and arithmetic error. The complex-number multiplications and additions/subtractions for FFT computation are implemented with LNS adders and look-up table (LUT) rather than using conventional two's complement multipliers and adders. Our design reduces the gate counts by 21% and the memory size by 16% when compared to the conventional two's complement implementation. Also, the estimated power consumption is reduced by about 18%. The LNS-based FFT processor synthesized with 0.35 ${\mu}m$ CMOS standard cell library has 39,910 gates and 2,880 bits memory. It can compute a 128-point FIT in 2.13 ${\mu}s$ with 60 MHz@2.5V, and has the average SQNR of 40.7 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.42-47
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• 2011

The partial product matrix (PPM) of a parallel squarer is symmetric. To reduce the depth of PPM, it can be folded, shifted and rearranged. In this paper, we present an area-efficient squarer design method using new partial product rearrangement. Also, a fixed-width squarer design method of the proposed squarer is presented. By simulations, it is shown that the proposed squarers lead to up to 17% reduction in area, 10% reduction in propagation delay and 10% reduction in power consumption compared with previous squarers. By using the proposed fixed-width squarers, the area, propagation delay and power consumption can be further reduced up to 30%, 16% and 28%, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.49-56
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• 2010

In this paper, a low-power frequency offset synchronization structure using CORDIC algorithm is proposed. Main blocks of frequency offset synchronization are estimation and compensation block. In the proposed frequency offset estimation block, implementation area is reduced by using sequential CORDIC, and throughput is accelerated by using 2 step CORDIC. In the proposed frequency offset compensation block, pipeline CORDIC is utilized for area reduction and high speed processing. Through MatLab simulation, function for proposed structure is verified. Proposed frequency offset synchronization structure is implemented by Verilog-HDL coding and implementation area is estimated by Synopsys logic synthesis tool.