Journal of the Institute of Electronics Engineers of Korea TC (대한전자공학회논문지TC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low-Power Frequency Offset Synchronization Block Design and Implementation using Pipeline CORDIC

Pipeline CORDIC을 이용한 저전력 주파수 옵셋 동기화기 설계 및 구현

  • 하준형 (상명대학교 컴퓨터정보통신공학과) ;
  • 정요성 ((주)다믈멀티미디어) ;
  • 조용훈 ((주)코메스타) ;
  • 장영범 (상명대학교 공과대학 정보통신공학과)
  • Received : 2010.01.01
  • Accepted : 2010.10.15
  • Published : 2010.10.25
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Abstract

In this paper, a low-power frequency offset synchronization structure using CORDIC algorithm is proposed. Main blocks of frequency offset synchronization are estimation and compensation block. In the proposed frequency offset estimation block, implementation area is reduced by using sequential CORDIC, and throughput is accelerated by using 2 step CORDIC. In the proposed frequency offset compensation block, pipeline CORDIC is utilized for area reduction and high speed processing. Through MatLab simulation, function for proposed structure is verified. Proposed frequency offset synchronization structure is implemented by Verilog-HDL coding and implementation area is estimated by Synopsys logic synthesis tool.

이 논문에서는 pipeline CORDIC(COordinate Rotation DIgital Computer)을 이용한 저전력 주파수 옵셋 동기화기 구조를 제안하였다. 주파수 옵셋 동기화기의 핵심 블록은 주파수 옵셋 추정부와 보상부이다. 제안된 주파수 옵셋 추정부에서는 sequential CORDIC을 사용하여 구현면적을 감소시켰으며 한번에 2 단계씩 CORDIC을 수행하는 방식을 사용하여 연산 속도를 높였다. 또한 제안된 주파수 옵셋 보상부에서는 pipeline CORDIC을 사용하여 구현면적을 줄임과 동시에 계산 속도를 향상시킬 수 있었다. MatLab을 사용하여 제안 구조가 주파수 옵셋을 추정 및 보상하는 function을 검증하였다. 제안 구조에 대하여 Verilog-HDL로 코딩하고 Synopsys tool을 사용하여 합성하여 구현면적을 실험하였다.

Keywords

References

  1. J. Granado, A. Torralba, J. Chavez, and V. Baena-Lecuyer, "Design of an efficient CORDIC-based architecture for synchronization in OFDM," IEEE Trans. Consum. Electron., vol. 52, No. 3, pp.774-782, Aug. 2006. https://doi.org/10.1109/TCE.2006.1706469
  2. A. R. S. Bahai, B. R. Saltzberg, and M. Ergen, "Multi-Carrier Digital Communications: Theory and Applications of OFDM", Springer, New York, 2004.
  3. K. I. Lee, J. Kim, J. Lee, and Y. S. Cho "A Compact CORDIC Algorithm for Synchronization of Carrier Frequency Offset in OFDM Modems," IEICE Trans. Commun. vol. E89-B, no. 3, pp. 952-954, Mar. 2006. https://doi.org/10.1093/ietcom/e89-b.3.952
  4. IEEE, Wireless MAC and PHY Specifications: High Speed Physical Layer in the 5 GHz Band, P802.11a.D7.0, July 1999.
  5. J. J. van de Beek, M. Sandell, and P. O. Borjesson, "ML estimation of time and frequency offset in OFDM systems," IEEE Trans. Signal Process., vol. 45, no. 7, pp. 1800-1805, Jul. 1997. https://doi.org/10.1109/78.599949
  6. Y. H. Hu, "CORDIC-based VLSI architectures for digital signal processing," IEEE Signal Process. Mag., vol.9, pp. 17-35, Jul. 1992.
  7. S. Chang and E. J. Powers, "An efficient frequency offset estimation in OFDM-based WALANS systems", Electronics Letters, vol 39, no. 21, pp. 1554-1555, 2003. https://doi.org/10.1049/el:20030920
  8. Z. R. Cheng, M. Gao, L. Li, D. Zhang, and Y. Song, "A design of modified CORDIC-based cosine and sine generator." IEEE 5th International Conference on ASIC, vol.2, pp. 765-768, Oct. 2003.