• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1867-1875
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• 2011

In this paper, a low-area 256-point FFT structure is proposed. For low-area implementation CSD(Canonic Signed Digit) multiplier method is chosen. Because multiplication type should be less for efficient CSD multiplier application to the FFT structure, the Radix-$4^2$ algorithm is chosen for those purposes. After, in the proposed structure, the number of multiplication type is minimized in each multiplication block, the CSD multipliers are applied for implementation of multiplication. Furthermore, in CSD multiplier implementation, cell-area is more reduced through common sub-expression sharing(CSS). The Verilog-HDL coding result shows 29.9% cell area reduction in the complex multiplication part and 12.54% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.147-150
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• 2007

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16$\times$16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35$\mu$m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1755-1762
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• 2016

In this paper, a small areal dual-output SC(switched capacitor) DC-DC converter with a improved range of an input voltage is presented. The conventional SC DC-DC converter has an advantage of low cost and small chip area. But, it has a narrow input voltage range to convert efficiently. Also, it has a lager chip area and a lower power efficiency from multiple outputs. The proposed SC DC-DC converter improves the power efficiency by using the capacitor array structure which efficiently converts the voltage according to the input voltage. By sharing two switch array, it reduces the number of switches and capacitors from 32 to 25. The proposed SC DC-DC converter was manufactured in a $0.18{\mu}m$ CMOS process. In the simulation, the range of the input voltage is 0.7~ 1.8V, the max. power efficiency is 90%, and the chip area is $0.255mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.67-74
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• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

• Proceedings of the Korea Water Resources Association Conference
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• 2019.05a
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• pp.189-189
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• 2019

도시화에 따른 토지이용패턴의 변화로 불투수면적이 증가하여 빗물의 침투량이 감소하고, 유출량은 증가하는 등 집중호우시 침수피해를 야기하게 된다. 또한 오염원의 증가로 수질오염과 지하수고갈에 따른 건천화 등 부정적 효과를 초래하는 것으로 알려져 있다. 최근 기후변화에 따라 물순환 체계가 변화하고 있으며, 이로 인해 도시의 홍수 및 가뭄이 극심해지고 시민의 삶의 질도 위협받고 있다. 우리나라의 경우 지속적으로 도시화 및 불투수면적이 증가하고 있으며, 집중호우의 발생빈도 또한 높아 심각한 수자원 물재와 홍수피해위험이 높다. 이에 도시의 물환경 변화 및 왜곡된 물순환 체계를 지속가능하도록 개선해야 할 필요성이 제기되었다. 환경부 및 국토부 등 정부기관에서는 물환경지속가능성을 위하여 저영향개발 기술요소를 도입하고 적용하고 있다. 본 연구에서는 침수위험지역의 저영향개발기법을 도입하여 유출저감 효과를 모의하고, 경제성 분석을 하였다. 본 연구의 대상지역은 경상남도 김해시 안동지구이며, 면적 364.2ha, 투수층면적 160.7ha, 불투수층면적 203.5ha로 불투수율은 55.90%로 산정되었다. 대상지역인 안동지구 우수관로현황 조사결과 (30년빈도 강우강도 적용) 관로의 통수능 검토시 전체관로 26.97km 중 통수능 부족관로는 15.60km로 전체대비 약 57.8%로 나타났다. 안동지구 내 우수관거는 간선관로의 경우 10년빈도, 지선관로의 경우 5년빈도로 설계, 시공되어 있으므로 각종 공단이 입지한 시가지인 안동지구는 도로포장등으로 인해 불투수층이 대부분을 차지해, 강우시 도로표면 유출수의 증대로 침수피해가 가중되는 것으로 판단되었다. 이에 저영향개발기법을 적용하여 맨홀로 유입되는 직접유출(DCIA, Directly Connected Impervious Area)를 줄이고, 유지관리 등을 고려하여 경제성을 평가하여 향후 침수위험지구 관거개량시 저영향개발기법을 활용할 수 있도록 하고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.8
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• pp.1839-1844
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• 2015

The low-density parity-check(LDPC) code has been adopted in many communication standards due to its error correcting performance, and the quasi-cyclic LDPC(QC-LDPC) is widely used because of implementation easiness. In the QC-LDPC decoder, a cyclic-shifter is required to rotate data in various sizes. This kind of cyclic-shifters are called multi-size circular shifter(MSCS), and this paper proposes a low-complexity structure for MSCS. In the conventional serially-placed two barrel-rotators, the unnecessary multiplexers are revealed and removed, leading to low-complexity. The experimental results show that the area is reduced by about 12%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.857-864
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• 2006

This paper describes a design of low-power/small-area arithmetic circuits which are vector processing unit powering nit, divider unit and square-root unit for mobile 3D graphic accelerator. To achieve area-efficient and low-power implementation that is an essential consideration for mobile environment, the fixed-point f[mat of 16.16 is adopted instead of conventional floating-point format. The vector processing unit is designed using redundant binary(RB) arithmetic. As a result, it can operate 30% faster and obtained gate count reduction of 10%, compared to the conventional methods which consist of four multipliers and three adders. The powering nit, divider unit and square-root nit are based on logarithm number system. The binary-to-logarithm converter is designed using combinational logic based on six-region approximation method. So, the powering mit, divider unit and square-root unit reduce gate count when compared with lookup table implementation.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.715-718
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• 1998

본 논문에서는 시분할 구조와 1.5bit 디지털 에러보상을 사용하여 작은 면적을 갖는 저 전압, 저전력 10bit 1㎒ 사이클릭 A/D 변환기를 제안하였다. 제안된 사이클릭 A/D 변환기는 시분할 구조를 사용함으로서 변환속도의 향상과 저 전력 특성을 가질 수 있었으며 1.5bit 디지털 에러 보상을 사용함으로서 10bit의 고해상도와 저 전력 특성을 구현할 수 있었다. 제안된 사이클릭 A/D 변환기는 0.6㎛ CMOS Nwell 공정 parameter로 simulation 하였으며 layout 결과 칩면적은 1.1㎜×0.8㎜ 이며 이는 비슷한 성능을 갖는 다른 A/D 변환기에 비하여 매우 작은 크기이다. 제안된 사이클릭 A/D 변환기는 3V의 전원전압에 1.6㎽의 전력소모를 갖는다. Matlab simulation 결과 INL, DNL은 각각 0.6LSB, 0.7LSB 이하의 값을 보였다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.414-418
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• 2016

In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.