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http://dx.doi.org/10.17661/jkiiect.2016.9.4.414

Low Complexity Gradient Magnitude Calculator Hardware Architecture Using Characteristic Analysis of Projection Vector and Hardware Resource Sharing  

Kim, WooSuk (Electrical, Electronic, and Control Engineering, HanKyong University)
Lee, Juseong (Center of Human-centered Interaction for Coexistence)
An, Ho-Myoung (Department of Electronics, Osan University)
Publication Information
The Journal of Korea Institute of Information, Electronics, and Communication Technology / v.9, no.4, 2016 , pp. 414-418 More about this Journal
Abstract
In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.
Keywords
Feature extraction; gradient magnitude calculator; high-throughput signal processing; low-complexity hardware architecture;
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1 A. Alaghi, C. Li and J. P. Hayes, "Stochastic circuits for real-time image processing applications", in Proc. ACM/EDAC/ IEEE Design Automation Conference (DAC), pp. 136:1-6, Jun. 2013.
2 P. Zhao, H. Zhu, H. Li, and T. Shibata, "A Directional-Edge-Based Real-Time Object Tracking System Employing Multiple Candidate-Location Generation", IEEE Transactions on Circuits and Systems for Video Technology, vol. 23, no. 3, pp. 503-517, Mar. 2013.   DOI
3 S. -L. Chen and E. -D. Ma, "VLSI Implementation of an Adaptive Edge-Enhanced Color Interpolation Processor for Real-Time Video Applications", IEEE Transactions on Circuits and Systems for Video Technology, vol. 24, no. 11, pp. 1982-1991, Nov. 2014.   DOI
4 P. R. Possa, S. A. Mahmoudi, N. Harb, C. Valderrama, and P. Maneback, "A Multi-Resolution FPGA-Based Architecture for Real-Time Edge and Corner Detection", IEEE Transactions on Computers, vol. 63, no.10, pp. 2376-238, Oct. 2014.   DOI
5 N. Kanopoulos, N. Vasanthavada, and R. L. Baker, "Design of an image edge detection filter using the Sobel operator", IEEE Journal of Solid-State Circuits, vol. 23, no. 2, pp. 358-367, Apr. 1988.   DOI
6 B. Geelen, F. Deboeverie, and P. Veelaert, "Implementation of Canny edge detection of Canny Edge Detection Filter for ITK Using CUDA", in Proc. IEEE Symposium on Computer Systems, pp. 33-40, Oct. 2012.