• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.5
• /
• pp.115-131
• /
• 2004

As dual port memories are being frequently used, test and diagnosis for dual port memories becomes more important. In this paper, anew diagnosis algerian which can classify faults in detail when the fault is detected during test process is developed. The new algerian increases its efficiency by using the information that can be obtained by test results as well as results using additional diagnostic pattern set. In addition the algorithm can diagnose various fault models for dual port memories.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.3
• /
• pp.20-33
• /
• 2002

As dual port RAMs are widely used in the various applications, the need for an efficient algorithm to diagnose faults in dual port RAMs is increased. In this paper we propose an efficient algorithm that can diagnose all kinds of faults in dual port RAMs. In addition, the new algorithm can distinguish various fault models and locate the position related to each fault. Using the new algorithm, fault diagnosis for dual port RAMs can be performed efficiently and the performance evaluation with previous approaches proves the efficiency of the new algorithm.

• Journal of KIISE:Computer Systems and Theory
• /
• v.28 no.6
• /
• pp.310-316
• /
• 2001

본 논문에서는 10N March 테스트 알고리즘에 기반한 내장된 이중 포트 메모리를 위한 효율적인 테스트 알고리즘을 제안하였다. 제안된 알고리즘은 각각의 포트에 대해 독립적으로 테스트 알고리즘을 적용함으로써 각각의 포트에 대해서 단일 포트 메모리 테스트 알고리즘을 적용하는 방법에 비해 시간 복잡도를 20N에서 8.5N으로 시간 복잡도를 줄였다. 그리고 제안된 알고리즘은 주소 디코더 고장, 고착 고장, 천이 고장, 반전 결합 고장, 동행 결합 고장을 모두 검출할 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.72-85
• /
• 2007

The development of memory design and process technology enabled the production of high density memory. However, this increased the complexity of the memory making memory testing more complicated, and as a result, it brought about an increase in memory testing costs. Effective memory test algorithm must detect various types of defects within a short testing time, and especially in the case of port memory test algorithm, it must be able to detect single port memory defects, and all the defects in the dual port memory. The March A2PF algorithm proposed in this paper is an effective test algorithm that detects all types of defects relating to the duel port and single port memory through the short 18N test pattern.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.1
• /
• pp.72-79
• /
• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.8
• /
• pp.22-34
• /
• 1999

In this paper, an efficient test algorithm for embedded dual-port memories is presented. The proposed test algorithm can be used to test embedded dual-port memories faster than the conventional multi-port test algorithms and can be used to completely detect stuck-at faults, transition faults and coupling faults which are major target faults in embedded memories. Also, in this work, BIST which performs the proposed memory testing algorithm is designed using Verilog-HDL, and simulation and synthesis for BIST are performed using Cadence Verilog-XL and Synopsys Design-Analyzer. It has been shown that the proposed test algorithm has high efficiency through experiments on various size of embedded memories.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.8
• /
• pp.55-62
• /
• 2012

The development of memory design and process technology enabled the production of high density memory. As the weight of embedded memory within aggregate Systems-On-Chips(SoC) gradually increases to 80-90% of the number of total transistors, the importance of testing embedded dual-port memories in SoC increases. This paper proposes a new micro-code based programmable memory Built-In Self-Test(PMBIST) architecture for dual-port memories that support test various test algorithms. In addition, various test algorithms including March based algorithms and dual-port memory test algorithms are efficiently programmed through the proposed algorithm instruction set. This PMBIST has an optimized hardware overhead, since test algorithm can be implemented with the minimum bits by the optimized algorithm instructions.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.2 s.332
• /
• pp.57-64
• /
• 2005

In this paper, we develop the common CAD tool that creates the automatically BIST IP by user settings for the convenient test of embedded memory. Previous tools have defect that when memory model is changed, BIST IP must re-designed depending on memory model because existing tools is limited the widely used algorithms. We develop the tool that is created automatic BIST IP. It applies the algorithm according to the memory model which user requests We usually use the multi-port asynchronous SRAM needless to refresh as the embedded memory. However, This work researches on the dual-port SRAM.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2013.11a
• /
• pp.46-47
• /
• 2013

지난 수십년 동안 휴대기기 시장의 다양한 요구에 맞추어 임베디드 시스템 기술이 발전되어 왔다. 현재의 임베디드 시스템은 작은 크기의 특화된 하드웨어를 차용하면서도 높은 효율의 성능을 저가에 제공할 수 있는 기술들이 핵심을 이루고 있다. 이러한 핵심 기술들 중의 하나가 다중 메모리 뱅크이다. 예를 들면, 이중 메모리 뱅크는 같은 공간에 두 배의 메모리 대역폭의 제공할 수 있는 특징을 갖는다. 이러한 특징은 이중포트 메모리에 비하여 적은 비용으로 동일한 대역폭을 제공할 수 있는 장점을 제공한다. 그러나 현재까지도 다중 메모리 뱅크의 효율적인 사용을 지원하는 소프트웨어 기술은 부족한 실정이다. 본 연구에서는 다중 메모리 뱅크의 활용 문제를 간섭 그래프 (interference graph)를 이용하여 효과적으로 해결하였다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.5C
• /
• pp.411-421
• /
• 2002

In this paper, we present a new survivor path memory management method and a dedicated hardware architecture for the design of high-speed Viterbi decoders in modern digital communication systems. In the proposed method, a novel use of k-starting node number deciding circuits enables to acheive the immediate traceback of the merged survivor path from which we can decode output bits, and results in smaller survivor path memory size and processing delay time than the previously known methods. Also, in the proposed method, the survivor path memory can be constructed with ease using a simple standard dual-ported memory since one read-pointer and one write-pointer, that are updated at the same rate, are required for managing the survivor path: the previously known algorithms require either complex k-ported memory structure or k-times faster read capability than write. With a moderate hardware cost for immediate traceback capability the proposed method is superior to the previously known methods for high-speed Viterbi decoding.