• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.680-682
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• 2000

이 논문은 에지와 정점에 고장이 있는 이중 루프 네트워크의 해밀톤 성질을 고려한다. 이중 루프 네트워크 G(mn;1,m)은 m$\times$n 그리드 그래프에 에지를 추가한 4-정규 그래프이다 m과 n이 모두 짝수인 이중 루프 네트워크G(mn;1,m)은 고장난 요소(에지와 정점)의 수가 1이하인 경우에 해밀톤 연결되어 있고, 고장난 요소의 수가 2이하인 경우에 항상 해밀톤 사이클을 가짐을 보인다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.819-825
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• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2001.11a
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• pp.198-201
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• 2001

L자형 루프를 이용하여 주파수대역이 6-18 GHz인 동축-이중릿지도파관 변환기를 상용 소프트웨어인 HFSS를 이용하여 설계한 후 제작하였다. L자형 루프는 동축-구형도파관 변환기에 이미 이용되고 있는 구조로써, 이를 동축-이중릿지도파관 변환기에 적용한 것이다. 제작 후 측정결과 대역폭이 6-18 GHz로 3:1 이상을 만족하며, 최대 삽입손실이 -1.52 dB 이었다.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.10
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• pp.868-879
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• 2000

이 논문은 에지나 정점, 혹은 모두에 고장이 있는 이중 루프 네트워크의 해밀톤 성질을 고려한다. 이중 루프 네트워크 G(mn;1,m)은 m$\times$m 그리드 그래프에 에지를 추가한 4-정규 그래프이다. m 과 n 이 모두 짝수인 이중 루프 네트워크 G(mn;1,m)은 고장난 요소(에지와 정점)의 수가 1이하인 경우에 해밀톤 연결되어 있고, 고장난 요소의 수가 2 이하인 경우에 항상 해밀톤 사이클을 가짐을 보인다.

• The Journal of the Acoustical Society of Korea
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• v.14 no.3
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• pp.28-36
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• 1995

In this paper, a double loop control model using leaky delay LMS algorithm are proposed for active noise control. The proposed double loop control model estimates the loudspeaker characteristic and the error path transfer function with on-line using only gain and acoustic time delay to reduce computation burden. The control of error signal through double loop control scheme makes the more robust cntrol system. The input signal of filter to estimate acoustic time delay is used difference between input signal of input microphone and adaptive filter output. And also, in nonstationary environments, the leaky delay LMS algorithm is employed to counteract parameter drift of delay LMS algorithm. For practical noise signal, the proposed double loop control model reduces noise level about 12.9 dB.

• Electronics and Telecommunications Trends
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• v.13 no.5 s.53
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• pp.53-64
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• 1998

본 고에서는 한파장 폐루프 공진기의 기본특성과 이를 활용한 이중모드 필터 구조 및 필터의 주요특징을 기술하였다. 또한 독립적인 직교공진모드를 이용한 폐루프 공진기의 특성과 공진기의 크기를 소형화 하는 기법 및 소형화 된 공진기의 공진조건 등을 기술하였고, 소형화 된 공진기를 이용한 듀플렉서의 응용 예 등에 대해 기술하였다. 폐루프 공진기를 이용한 이중모드필터 등은 마이크로 스트립 형태로 구현이 가능하기 때문에 MIC 또는 MMIC 등에 적합한 구조이며, 능동소자 등의 삽입이 가능하기 때문에 능동필터, VCO, 튜닝필터 등의 구현이 가능하고 소형의 듀플렉서 설계가 가능하기 때문에 향후 마이크로파 부품분야에서 기대되는 부품이라 할 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.65-70
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• 2008

A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.912-920
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• 2003

This paper is about the design of a small wide-band slot loop antenna, which consists of dual offset-fed and rectangular loop within the slot on a substrate. The proposed antenna is a novel structure generating a multi-resonances due to three geometrical resonance structures. The impedance matching of this antenna can be accomplished by changing the offset position of dual-fed at resonance frequencies. In this experiment, the slot of a fabricated antenna has a center frequency of 6.755㎓, 12.5mm${\times}$50mm in size and the rectangular loop has 10.5mm${\times}$27.5mm in size. The measured result is fractional bandwidth 63.21% with VSWR 2:1, which is agreed with the simulated result within 5% of error, and the maximum antenna gain is 7.42㏈i.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.191-200
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• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.899-905
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• 2017

This paper presents a reference-less dual loop clock and data recovery (CDR) circuit that supports a data rate of 2.496 Gb/s for the mobile industry processor interface (MIPI) M-PHY. An adaptive loop bandwidth scheme is used to implement the fast lock time maintaining a low time jitter. To this scheme, the proposed CDR consists of two loops for a frequency locked loop and a phase locked loop. The proposed 2.496 Gb/s reference-less dual loop CDR is designed using a 65 nm CMOS process with 1.2 V supply voltage. The simulated peak-to-peak jitter of output clock is 9.26 ps for the input data of 2.496 Gb/s pseudo-random binary sequence (PRBS) 15. The active area and power consumption of the implemented CDR are $470{\times}400{\mu}m^2$ and 6.49 mW, respectively.