• Journal of the Computational Structural Engineering Institute of Korea
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• v.28 no.1
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• pp.63-69
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• 2015

In this paper, infrared reflector design targeting infrared stealth effect is presented using structural optimization based on the phase field method. The analysis model was determined to accomplish the design that an incident infrared wave was reflected to a desired direction. The design process was to maximize the objective value at the measuring domain located in a target region and the design objective was set to the Poynting vector value which represents the energy flux. Optimization results were obtained according to the variation of some parameter values related to the phase field method. The model with a maximum objective value was selected as the final optimal model. The optimal model was modified to eliminate the gray scale using the cut-off method and it confirmed improved performance. In addition, to check the desired effect in the middle wave infrared range(MWIR), the analysis was performed by changing the input wavelength. The finite element analysis and optimization process were performed by using the commercial package COMSOL combined with the Matlab programming.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.9
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• pp.973-978
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• 2014

This study focused on the design of the reflecting layer of a light trapping system fora thin film solar cell using topology optimization based on the phase field method. Therefore, incident light was caused to propagate in the desired direction by reflecting it from this layer, which is the design domain. The same method was applied to the conceptual design of an infrared stealth structure in near infrared range. The results using the phase field method were compared with those using the density method. The design objective was to maximize the Poynting vector value representing the energy flux, which was measured in a measuring domain to control the reflected wave direction. A finite element analysis and optimization process were performed using the commercial package COMSOL combined with the MATLAB programming.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.254-256
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• 2019

소수체 GF(p)와 이진체 $GF(2^m)$ 상의 다중 타원곡선을 지원하는 듀얼 필드 ECC (DF-ECC) 프로세서를 설계하였다. DF-ECC 프로세서의 저면적 설와 다양한 타원곡선의 지원이 가능하도록 워드 기반 몽고메리 곱셈 알고리듬을 적용한 유한체 곱셈기를 저면적으로 설계하였으며, 페르마의 소정리(Fermat's little theorem)를 유한체 곱셈기에 적용하여 유한체 나눗셈을 구현하였다. 설계된 DF-ECC 프로세서는 스칼라 곱셈과 점 연산, 그리고 모듈러 연산 기능을 가져 다양한 공개키 암호 프로토콜에 응용이 가능하며, 유한체 및 모듈러 연산에 적용되는 파라미터를 내부 연산으로 생성하여 다양한 표준의 타원곡선을 지원하도록 하였다. 설계된 DF-ECC는 FPGA 구현을 하드웨어 동작을 검증하였으며, 0.18-um CMOS 셀 라이브러리로 합성한 결과 22,262 GEs (gate equivalences)와 11 kbit RAM으로 구현되었으며, 최대 100 MHz의 동작 주파수를 갖는다. 설계된 DF-ECC 프로세서의 연산성능은 B-163 Koblitz 타원곡선의 경우 스칼라 곱셈 연산에 885,044 클록 사이클이 소요되며, B-571 슈도랜덤 타원곡선의 스칼라 곱셈에는 25,040,625 사이클이 소요된다.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.277-280
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• 2002

This paper analyze the characteristics of three multipliers in finite fields GF(2m) from the point of view of processing time and area complexity. First, we analyze structure of three multipliers; 1) LSB-first systolic array, 2) LFSR structure, and 3) CA structure. To make performance analysis, each multiplier was modeled in VHDL and was synthesized for FPGA implementation. The simulation results show that LFSR structure is best from the point of view of area complexity, and LSB systolic array is best from the point of view of processing time per clock.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.415-417
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• 2003

본 논문에서는 유한 필드 GF(2$^{m}$ ) 상에서 A$B^2$연산을 수행하는 디지트 시리얼(digit-serial) 시스톨릭 구조를 제안하였다. 제안한 구조는 디지트 크기를 적당히 선택했을 때, 비트-패러럴(bit-parallel) 구조에 비해 적은 하드웨어를 사용하고 비트-시리얼(bit-serial) 구조에 비해 빠르다 또한, 제안한 디지트 시리얼 구조에 파이프라인 기법을 적용하면 그렇지 않은 구조에 비해 m=160, L=2 일 때 공간-시간 복잡도가 10.9% 적다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.4
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• pp.653-660
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• 1998

The purpose of this paper is to analyze the electromagnetic field characteristics of microstrip array antenna with the FDTD(finite difference-time domain method). Finite difference equations of Maxwell's equations are defined in rectangular coordinate systems. To simulate the unbounded problem like a free space, the Mur's absorbing boundary condition is also used. After modeling the microstrip array antenna with the grid structure, the transient response of the field distribution is depicted in the time domain.

• Journal of the Korean Magnetics Society
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• v.18 no.3
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• pp.103-108
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• 2008

Magnetoresistive random access memory (MRAM) don't get very public face on the field of non-volatile memory. Because recording capacity of MRAM is smaller than other non-volatile memory and structurally, magnetic efficiency of MRAM is very bad. We diminish a size of one cell in order to make MRAM of high recording capacity. But It don't make high recording field in general structures consisting of two current wire. Accordingly, We make a cell of small size is impossible. In this paper, we suggest new MRAM that it have two pole of high permeability on both ends of recording layer. Because magnetic efficiency of new MRAM is higher than exiting MRAM, it can make high recording field. And we can diminish the size of one cell due to recording layer of high coercivity. We used three-dimension finite element method to prove the reliability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.625-631
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• 2002

This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.

• Journal of the Korea Society of Computer and Information
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• v.20 no.2
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• pp.1-10
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• 2015

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.27-35
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• 2004

Finite or Galois fields have been used in numerous applications such as error correcting codes, digital signal processing and cryptography. These applications often require exponetiation on GF(2$^{m}$ ) which is a very computationally intensive operation. Most of the existing methods implemented the exponetiation by iterative methods using repeated multiplications, which leads to much computational load, or needed much hardware cost because of their structural complexity in implementing. In this paper, we present an effective VLSI architecture for exponentiation on GF(2$^{m}$ ). This circuit computes the exponentiation by multiplying product terms, each of which corresponds to an exponent bit. Until now use of this type algorithm has been confined to a primitive element but we generalize it to any elements in GF(2$^{m}$ ).